SoC Modeling Experts: High Level Synthesis: C, C++, SystemC

Positions:
SoC Modeling Experts: High Level Synthesis: C, C++, SystemC
You will be part of the next wave in design & verification of SoC at higher level of abstraction using C, C++, SystemC based HLS methodology

Location: Noida, Bangalore

Job Description:
The candidate will be involved in any of the following activities:

• Design and verification of semiconductor chips at higher level of abstraction
• Design and implement hardware-accelerated solutions for FPFA / ASIC / SoC
• Design and develop design algorithms in C/C++/SystemC for efficient HW implementation
• Architect and implement accelerator modules using high-level synthesis (HLS) tools
• Develop, test, maintain and improve HLS based designs & methodologies

Desired Skills and Experience:​

• Bachelors in EC / CS from a reputed university
• 1-6 years experience in Front End ASIC/FPGA design flows using High-Level Synthesis
• Proficiency in C / C++ , Data structures, Algorithms, OOPS concepts
• Exposure to any HDL: SystemC, Verilog, System Verilog
• Exposure to scripting language: Python, Perl, TCL/TK
• Experience with one/more of the HLS tools: Mentor Catapult-HLS, Xilinx Vivado HLS, Cadence Stratus

Preferred Expertise:

• Exposure to implementing algorithms for Video processing, Image processing, Audio Processing, Speech synthesis, 5G etc..
• Exposure to Synthesis, Simulation and other design verification methodologies
• Experienced with FPGA design flow and creating high-performance designs on FPGAs
• Ability to translate problems into hardware solutions