CEO Interview: YJ Su of Anaglobe

AnaGlobe Technology, Inc. is a leader in layout integration solutions that have been adopted by world-wide technology leading companies including the foundries, fabless, design services, packaging, panel, and IP companies. I know several of Anaglobe’s customers and am happy to work with them, absolutely.

The following is a Q&A discussion with YJ Su of AnaGlobe:

Please tell us about AnaGlobe?
AnaGlobe is a Taiwanese EDA company based in Hsinchu. We specialize in layout especially with custom layout creation and wafer-level chip-scale layout integration. We have been collaborating with several world-class semiconductor companies for more than 10 years, including customers in the US, Ireland, China, Korea, Japan, Singapore and Taiwan. We have distributors in the US, Europe, China, Korea, Japan and South-East Asia. AnaGlobe will exhibit at DAC 2018, booth #2340.

What makes AnaGlobe unique?
AnaGlobe offers a versatile IC layout framework and closely work with customers to embrace the fast-pace and timely response to the dynamic nature of top semiconductor foundries, design houses and packaging services providers. AnaGlobe has been working closely and responded rapidly to our customers’ demands, and expect to grow with customers’ in multi-wins collaborations.

AnaGlobe also sponsors some talented EDA researchers and projects in Taiwan. We though start with a small-scale company, but also do some state-of-the-art topics and have participated leading-edge technologies such as pattern matching, machine learning, etc. in IC layout domains.

What keepslayout integration engineers up at night?
Today’s semiconductor industry faces the dynamic dilemma among both economic and technology factors, e.g. time-to-market, ROI estimation (return-on-investment), with various process nodes, SOC or SIP path-finding and diversity of the end products such as applications in IoT, automotive, mobile and high performance computing and even heterogeneous components integration.

One common challenge to layout integration team is facing the dynamic nature of complicated design intents, revisions and huge data size. For example, a top-level layout assembly task normally manages hundreds of sub-blocks in either a SOC GPU chip, or an advanced-node testchip design or a multi-chip SIP project, while each sub-block owner may have many design re-spins. These require high performance layout integration platform, though not necessarily as-is expensive design implementation or signoff EDA options. As we’ve been engaging these with top-tier fabless, foundries and packaging houses, AnaGlobe commit this topic is good fit to our software strengths and decent technical customization supports, for multi-wins scenarios.

How can AnaGlobe products help?
We have two main products: GOLF aims at full custom layout creation with high flexibility; THUNDER eyes on wider diversities with great performance (e.g. terabytes data capability), from IPs to wafer-level chip-scale layout assembly integration. Furthermore, with flow automation and CAD features combination, we can build comprehensive database handling solutions in tape out flows, chip-packaging integration and path-finding, and even inline manufacturing image-to-cad inspection analysis domains.

GOLF:
For custom layout creation, we offer three levels of functionality:

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• Being a SI2 member, our tools are built-in OA (OpenAccess) database compatible, with proprietary data structure of GDS/OASIS/DXF/EDIF import/export. GOLF provides layout and schematic viewing, layout editing, hierarchical editing, query, undo/redo, schematic-driven layout (SDL) and also interface to major verification tools (Calibre and ICV).
• Instead of tedious programming language to create PCell layout, GOLF (Geometric Objects Layout Formula) offers flexible and highly productive device-level layout creation and reusable hierarchical layout generator on OpenAccess, by both programming support (API for TCL, Python and Perl) and a GUI-based PCell Designer. It is an intuitive IDE (integrated development environment) for PCell creation, preview, testing, debug, and documentation on layout directly. Customers also adapt PCell Designer in the creation of manufacturing test key layout, flat panel display layout and 3D packaging layout, etc.
• GOLF is also incorporated with several constraint-driven custom placers and routers, for specific application of examples, characterization test chip layout generator in advanced process nodes, all-angle router for free-form panel display, constraint-driven analog layout, and so on.THUNDER:
  For wafer-level chip-scale layout integration, our goal is to support the layout database from post P&R, IP merge, verification (XOR LVL, connectivity, etc.), debugging, defect inspection, failure analysis to chip-package integration. Comparing to normal OA file size handling capability, THUNDER has a proprietary database, called ThunderDB, and is capable to handle huge layout data with extreme performance of up to 600+GB GDS per minute. Users can then perform big data analysis for further processing (e.g. 3D-view, cross-section, density map, wafer map), machine learning based optimization, and read/write for GDS, OASIS, LEF/DEF, MEBES and OpenAccess.Can you provide some real world (customer based) examples?
  Generally, our customers include some of the top 10 ranking companies of IC foundries, OSATs, IC design houses, optoelectronics companies and even semiconductor equipment vendors. GOLF has been used in the layout creation of test structures for advanced process technology nodes, free-form panel displays, 3D packaging and analog designs. THUNDER has been tailored into a variety of applications including an in-house collaboration platform, a 2.5D/3D packaging layout integration flow, sign-off tape out flows and the layout data preparation front-end of e-beam equipment.

  For example, the IP merge and the XOR LVL functions of THUNDER have been adopted by several customers in their sign-off tape out flows and obtained 10x performance gain. Some of our customers use THUNDER to handle multiple data sources (e.g. layout data, DRC results, pictures from SEM, in hundreds of GB scale) to analyze the data sanity.

  Which markets do you feel offer the best opportunities for AnaGlobeproducts the next few years and why?
  We may recap our versatile layout platform positions good fit for both cell bottom-up design flows (mainly with GOLF) and system top-down design flows (mainly with THUNDER). In addition to GOLF user-friendly PCell creation, schematic and/or constraint-driven layout editing, THUNDER’s capability in huge design handling, efficient database structure, flexible flows automation and interface to major verification EDA tools also ensure the seamless design flows to confront the dynamic design efforts in IoT, automotive, mobile and high performance computing applications. AnaGlobe keeps spending tremendous efforts to develop advanced layout functions in the very near future, and commits to facilitating the whole design solutions.

  http://www.anaglobe.com/

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