PCI Express Wiki

PCI Express (PCIe) is a high-speed serial computer expansion bus standard designed to replace older bus standards such as PCI, PCI-X, and AGP. It is used for connecting high-performance hardware devices like graphics cards, SSDs, Wi-Fi cards, Ethernet adapters, and AI accelerators to a motherboard.

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Overview

• Full Name: Peripheral Component Interconnect Express

• Initial Release: 2003

• Maintained By: PCI-SIG (PCI Special Interest Group)

• Latest Version: PCIe 6.0 (released in 2022); PCIe 7.0 (announced for 2025)

• Key Features: High-speed data transfer, scalability, low latency, compatibility with older standards.

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Technical Architecture

PCIe uses a point-to-point architecture with serial lanes rather than the shared parallel bus architecture used by PCI. Each lane consists of two differential signaling pairs: one for sending and one for receiving data.

• Lane Configuration: x1, x2, x4, x8, x16, x32

• Data Rate (per lane per direction):

  • PCIe 1.0: 250 MB/s

  • PCIe 2.0: 500 MB/s

  • PCIe 3.0: 1 GB/s

  • PCIe 4.0: 2 GB/s

  • PCIe 5.0: 4 GB/s

  • PCIe 6.0: 8 GB/s (with PAM4 signaling)

  • PCIe 7.0: 16 GB/s (targeted)

Each subsequent version has typically doubled the data rate while maintaining backward compatibility.

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Key Components

• Root Complex (RC): Interfaces between the CPU/memory subsystem and PCIe devices.

• Switches: Allow multiple devices to communicate over a single PCIe interface.

• Endpoints: The actual devices (e.g., GPU, SSD) that connect to the PCIe bus.

• Bridges: Used to connect legacy PCI devices to PCIe systems.

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Signaling & Protocol Layers

PCIe consists of three main layers:

1. Transaction Layer: Responsible for packet creation and addressing.

2. Data Link Layer: Ensures data integrity with error detection and retransmission.

3. Physical Layer: Handles actual transmission of bits over the wire.

Newer generations (like PCIe 6.0 and 7.0) adopt PAM4 (Pulse-Amplitude Modulation with 4 levels) signaling instead of traditional NRZ (non-return-to-zero) to achieve higher throughput.

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Use Cases

• Consumer PCs: High-performance GPUs, NVMe SSDs, and network cards.

• Servers and Data Centers: Accelerators (e.g., NVIDIA GPUs, FPGAs), RAID cards, SmartNICs.

• Embedded Systems: Industrial controllers, robotics, automotive infotainment.

• AI and HPC Workloads: PCIe is critical for interconnecting GPUs and high-speed storage.

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Form Factors & Interfaces

• Add-in Cards: Standard x1, x4, x8, x16 slots found on motherboards.

• M.2: A compact form factor often used for SSDs (e.g., NVMe drives).

• U.2 and EDSFF: Interfaces used in enterprise storage systems.

• CXL (Compute Express Link): An emerging interconnect built on PCIe 5.0/6.0 physical layer for memory coherency and AI acceleration.

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Backward and Forward Compatibility

PCIe maintains software and mechanical backward compatibility, allowing newer cards to operate in older slots (with reduced speed) and vice versa, within physical and power constraints.

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Power Management

PCIe includes Active State Power Management (ASPM) and supports various low-power states (L0s, L1, L2, etc.), making it suitable for mobile and embedded applications.

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Comparison with Other Interconnects

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Future Roadmap

• PCIe 7.0 (2025/2026):

  • 512 GB/s aggregate bandwidth for x16

  • PAM4 signaling with higher energy efficiency

  • Further reduction in latency and support for AI/HPC applications

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PCI-SIG and Ecosystem

The PCI Special Interest Group (PCI-SIG) governs the PCIe specification and includes members from across the semiconductor and computing industries, such as Intel, AMD, NVIDIA, Broadcom, Marvell, and others.

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Challenges

• Signal Integrity at Higher Speeds: Requires advanced PCB materials and layout.

• Power Consumption: Particularly relevant for mobile and data center environments.

• Latency Sensitivity: For real-time workloads and memory coherency, solutions like CXL are augmenting PCIe.

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