Samsung X-Cube™ (eXtended-Cube)

Samsung X-Cube™ is a 3D IC packaging technology developed by Samsung Electronics that enables vertical stacking of multiple active logic dies using through-silicon vias (TSVs) and micro-bump bonding. As part of Samsung’s Advanced Package (AVP) portfolio—which also includes I-Cube™ (2.5D interposer-based packaging) and H-Cube™ (high-performance substrate solutions)—X-Cube is designed to deliver higher bandwidth, better power efficiency, and smaller form factors for high-performance computing (HPC), AI, networking, and mobile applications.

Samsung first announced X-Cube in August 2020, with test silicon based on 7nm FinFET and demonstrated a logic-on-logic stacking architecture. It is a key enabler of Samsung’s chiplet strategy, aiming to compete with Intel’s Foveros and TSMC’s SoIC™ in the growing market for heterogeneous integration.

Overview

X-Cube enables active die stacking, where a logic die is vertically mounted on top of another logic die using TSVs and micro-bumps, allowing dense interconnects and compact system design. Unlike passive interposer-based technologies (like I-Cube), X-Cube allows functional logic dies to interact at ultra-short distances, significantly reducing latency and interconnect power while increasing bandwidth.

X-Cube supports heterogeneous chip integration—allowing different IP blocks, process nodes, or design houses to be combined into a modular, 3D chiplet system.

Key Features

Feature	Description
3D IC Stacking	Active logic-on-logic stacking via TSV and micro-bump
TSV-based Interconnect	Through-silicon vias for vertical signal and power routing
High Bandwidth	Short vertical interconnects enable >2 Tbps/mm bandwidth potential
Low Power	Reduced interconnect lengths lower energy per bit transferred
Heterogeneous Integration	Stack different IPs or process nodes (e.g., logic + SRAM)
Compact Form Factor	Enables ultra-dense packages for HPC and mobile
Foundry + Packaging Integration	Vertical integration across fab and AVP business units

How Samsung X-Cube Works

A bottom logic die (e.g., SoC base layer) is fabricated with TSV holes and contact pads for vertical interconnects.
One or more top dies (e.g., SRAM, AI accelerator) are separately fabricated and prepared with micro-bumps.
The top die is precisely aligned and bonded face-down to the bottom die using fine-pitch micro-bumps.
TSVs provide vertical electrical connections through the die stack.
The entire 3D stack is mounted on an organic or interposer-based package substrate and connected to the PCB.

Applications

High-Performance Computing (HPC): CPUs with stacked cache or accelerators
AI and Machine Learning: Logic + SRAM/DRAM + AI core stacking
Networking and Data Center: Compact, low-power interconnects
Mobile SoCs: Thin, energy-efficient integration of application processors and memory
Automotive and Edge AI: Rugged 3D packaging for inference engines

Samsung X-Cube vs Other Technologies

Feature	Samsung X-Cube	Intel Foveros	TSMC SoIC	CoWoS	EMIB
Type	3D	3D	3D	2.5D	2.5D
Stacking	Logic-on-logic	Logic-on-logic	Logic-on-logic	Side-by-side	Side-by-side
TSVs	Yes	Yes	Yes	Yes	No
Interposer	No	No	No	Yes	Embedded bridge
Bandwidth	Very High	Very High	Ultra High	High	High
Cost	High	High	High	Higher	Medium
First Use	2020 (demo)	2019	2021	2012	2017

Integration with Other Samsung Technologies

X-Cube complements Samsung’s broader Advanced Package (AVP) portfolio:

I-Cube™: 2.5D package with silicon interposer (e.g., logic + HBM)
H-Cube™: Organic substrate with high-layer count for HPC and memory-rich packages
SAINT™: Samsung’s in-house advanced packaging design platform
HBM: X-Cube can be co-packaged with HBM2E, HBM3, or future HBM4 memory

Samsung envisions future 3D SoC platforms that combine:

Compute tiles (e.g., Arm CPU, AI accelerators)
Cache dies (e.g., stacked SRAM)
Memory (e.g., HBM, LPDDR)
IO and analog dies (e.g., PCIe, SerDes)

Design Enablement and Foundry Services

X-Cube is supported by Samsung Foundry Design Kit (FDK)
Partnered with major EDA vendors (Cadence, Synopsys, Siemens) for 3D IC flows
Enables floorplanning, thermal simulation, timing signoff, and TSV-aware LVS/DRC
Part of Samsung’s SAFE™ (Samsung Advanced Foundry Ecosystem), including IP, EDA, and packaging

Advantages

Ultra-high bandwidth inter-die connections
Reduced power consumption for interconnects
Area-efficient stacking for compact systems
Enables reuse and modularity in SoC design
Integrated flow from Samsung Foundry to AVP

Challenges

Thermal management in stacked logic dies
Yield sensitivity due to stacking of known-good dies
TSV process complexity
EDA support for timing, IR-drop, and mechanical reliability
Cost compared to monolithic or 2.5D solutions

Future Directions

X-Cube 2.0 with hybrid bonding for sub-10μm pitch
Integration with co-packaged optics and chiplet ecosystems
Support for UCIe (Universal Chiplet Interconnect Express)
More layers and larger 3D stacks for exascale computing
Greater synergy with gate-all-around (GAA) transistor nodes like SF3 and SF2