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Carbonize your Imagination

Carbonize your Imagination
by Paul McLellan on 06-13-2012 at 7:00 am
Categories: EDA, Imagination Technologies, IP

Just up the road from Cambridge-based ARM in Kings Langley is Imagination Technologies, their biggest competitor in the GPU market. Interestingly they also were a customer of VLSI Technology in the early days back when they were called Videologic. Tomorrow, jointly with Carbon, they are announcing that a wide range of their PowerVR, Ensigma and Meta core IP will be available as 100% accurate virtual models from Carbon’s IP Exchange web portal.

Subject to approval from Carbon and Imagination (I’m guessing ARM need not apply!) users can download the models from the portal and drop them onto the design canvas. You can then do architectural design, pre-silicon firmware development and all the usual stuff for which virtual platforms are great.

More and more chips involve multimedia. Probably the most famous customer of Imagination is Apple: theirs is the GPU used in both the iPhone and the iPad. Funnily enough Apple doesn’t appear in their list of licensees on their website, I guess even though everyone knows that is what is in A4 and A5 (I believe Apple has actually said so) they still aren’t allowed to use the logo. But Imagination have other non-GPU cores for other markets too.

The models are implemented by Carbon using master data supplied by Imagination. This uses the same compiler to generate them from RTL as is used for ARM mdoels. But users can generate their own ARM models at the portal. The Imagination models are handcrafted on request (and require Imaginations permission).

Models available include:

  • PowerVR Series5, Series5XT and Series6 family of Graphics Processing Units (GPU)
  • PowerVR Series3 VXD and VXE families of video decoders and encoders
  • Ensigma Series3 UCCP family of multi-standard receivers and Wi-Fi/Bluetooth connectivity
  • Meta Series2 hardware multi-threaded SoC processors

Carbon’s website is here. Carbon IP Exchange is here.
Imagination’s website is here.

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How to Use Those Licenses Effectively

How to Use Those Licenses Effectively
by Paul McLellan on 06-12-2012 at 8:05 pm
Categories: EDA

So DAC is over and you are no longer thinking about the features and benefits of new tools or even the tools that you already own. But once you have lots of tools then you need to worry about how to use them efficiently.

But here are three things that you need to worry about to get the most out of your EDA investment:

  • how do you measure the actual license usage?
  • how do you build best of breed flows to encapsulate the tools you have invested in?
  • how do you maximize the use of the licenses you have invested in?

This is increasingly important since both the scale of the hardware infrastructure (server farms, perhaps with a wide range of different machines) and the scale of the jobs themselves (huge number of runs) are enormous.

Runtime Design Automation (RTDA) has three tools that address the three problems above and which scale to the size of the infrastructure and the jobs.

LicenseMonitor is a tool for gathering data on license usage and displaying it in useful intuitive ways. It operates with most license managers such as FlexLM.

FlowTracer captures all the details of a flow and so allows best-in-class flows to be created and deployed across an organization.

NetworkComputer is the fastest available commercial job scheduler. It interfaces with license managers to make efficient use of the licenses and can even statistically over-schedule. It can share licenses across an organization based on demand and policies, and use pre-emption to ensure licenses are allocated to important jobs (such as designs nearing tapeout).

As an example, RTDA told me about a typical timing run that a customer would make. It is a block flow of timing runs with 45 timing corners multiplied by plain/noise/interface-logic-models making 135 jobs in parallel (and 144 for the full-chip runs). This is completely distributed across a farm taking into account availability of both servers and licenses.

Download the LicenseMonitor datasheet.
Download the FlowTracer datasheet.
Download the NetworkComputer datasheet.

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Jasper’s Kathryn Kranen Elected EDAC Chairman

Jasper’s Kathryn Kranen Elected EDAC Chairman
by Paul McLellan on 06-12-2012 at 8:05 pm
Categories: EDA


Kathryn Kranen, CEO of Jasper was elected chairman of EDAC for 2012-2014. She has has 20 years EDA industry. She started her career as a design engineer at Rockwell International and then joined Daisy Systems (one of the DMV, the second generation of EDA companies). She then moved to be VP of North American sales at Quickturn (emulation) before becoming CEO of Verisity Design.

Wally Rhines (Mentor) and Lip-Bu Tan (Cadence) were elected vice-chairmen.
The other directors are Raul Camposano (Nimbic), Ed Cheng (Gradient), Dane Collins (AWR), Aart de Geus (Synopys), Dean Drako (IC Manage), John Kibarian (PDF Solutions), Simon Segars (ARM) and Ravi Subramaniam (BDA).

The EDAC press release is here.

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BDA TSMC Theater Presentation

BDA TSMC Theater Presentation
by Daniel Nenni on 06-12-2012 at 5:00 pm
Categories: EDA, Foundries, TSMC

I caught the Berkeley Design Automation presentation in the TSMC Theater, where Simon Young (BDA’s director of product marketing) described the Analog FastSPICE (AFS) nanometer circuit verification platform, built on their foundation of very fast, very accurate, high capacity circuit simulation.

BDA claims the AFS platform offers the fastest and most accurate circuit simulation, with single-core performance 5x to 10x faster than other foundry-certified simulators, and up to a further 4x faster with multithreading. AFS is consistently endorsed by designers of data converters, PLLs and DLLs, SerDes and other high-speed I/O, RFCMOS, and CMOS image sensors.

AFS is certified on several TSMC process technologies from 65nm down to 20nm through the TSMC SPICE-Qualification Program. In addition, BDA and TSMC have for several years collaborated on the device noise sub-flow for the TSMC analog and mixed-signal reference flow. Together the two companies qualified AFS’s full-spectrum transient noise analysis for this flow. A great many transient simulations are needed for this qualification process, including MOS white and flicker noise sources. Very close correlation to silicon is necessary for certification to be granted. These steps are repeated for a variety of complex mixed-signal IPs, including ADCs and PLLs.

Two recent customer example circuits illustrate the value of this qualification. Firstly, a closed-loop 14GHz PLL circuit from Analog Bits, designed for 100GbE applications, passed through performance signoff with AFS transient noise. Correlation between transient noise simulation and silicon was within 2dB. A second circuit, a delta-sigma ADC from Qualcomm, exhibited a 25dB increase in SNDR when AFS simulations including transient noise were run. Correlation between transient noise simulation and silicon was within 1.5dB. Many other examples were share last fall, at BDA’s nanometer Circuit Verification Forum.

AFS’s numerical noise floor is well below 160dB. Nanometer circuit designers demanding high dynamic range and high noise bandwidth value this accuracy. SPICE simulators achieve 60dB dynamic range with default settings, so tightening tolerances is required for trustworthy performance signoff of innovative architectures on nanometer process technologies.

Contrary to digital fastSPICE simulators that use table lookup models and an event-driven algorithm to deliver speed and capacity at the cost of accuracy, Simon compared the AFS Circuit Simulator to foundry-endorsed “sign-off” SPICE simulators. AFS solves the device analytical equations and the full matrix every simulation time-step. The difference is that tightening simulation tolerances doesn’t cause AFS to slow-down in the same way that other simulators do. And AFS always converges on a DC solution and runs transient simulation quickly, even for circuits above 10M elements.

For all this accuracy and speed, some designers want to run fast functional verification and don’t need nanometer SPICE accurate results. AFS offers a combination of user-selectable options to relax tolerances, simplify models, and simplify netlists (with RC reduction, for example). With these options set, AFS performance increases by another 4x to 5x.

Clearly, for nanometer accurate circuit simulation, 5x to 10x — or more — faster than alternatives, for large and complex circuits of 10M elements, foundry-certified AFS offers a great solution.

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Ausdia’s Timevision

Ausdia’s Timevision
by Paul McLellan on 06-11-2012 at 8:05 pm
Categories: EDA
1 Comment

I met Sam Appleton of Ausdia during DAC. I found it quite hard to understand exactly what they do. I’ve talked before about something that I nick-named City Slickers’ Marketing. It is named after the following exchange from the movie City Slickers:Curly: Do you know what the secret of life is? [holds up one finger] This.
Mitch: Your finger?
Curly: One thing. Just one thing. You stick to that and the rest don’t mean shit.
Mitch: But, what is the “one thing?”
Curly: [smiles]That’s what you have to find out.

Sometimes this amounts to making sure that you have the right product and sometimes this means making sure that you have the right explanation and positioning. If you can’t have a good elevator pitch to a VP engineering at a customer then your product is going to be hard and timeconsuming to sell (and by the way, talking of elevator pitches, Sand Hill Road doesn’t really have elevators since there are no towers).

Ausdia has some of this latter problem. What they do, the niche they fill, is hard to explain simply. I think I get it but I’m not completely sure.

Timevision is a product used along with a static timing tool (such as Synopsys’s PrimeTime). The reality is that a modern design has tens if not hundreds of millions of instances, power down regions, multiple clock domains, scan test and more. If you don’t have a completely solid set of timing constraints, a good understanding of the clock architecture, power architecture, false paths and so on then you are going to end up with gigabytes of data that is pretty much impossible to interpret.

Timevision is a tool to address this that adds intelligence into how the static timing tool is driven. It can deduce a lot from just examining the netlist but the more information you give it the more powerful it gets and the more useful the output from STA will be. Under the hood it has formal techniques for deducing what is going on in your design without having to be told everything. So instead of having to write thousands of lines of timing constraints, they are synthesized and deduced from the design itself along with a small amount of steering information.

A particular challenge with static timing is that a lot is done right at the end of the design. Problems here don’t have any schedule flexibility to make up for time lost while closing timing for the design. So it is doubly important to make sure that you have good constraints by the time tapeout approaches.

Ausdia is a privately held company, obviously. Less obviously it has no external investors and has been completely bootstrapped. It was formed in late 2006 and started product development in 2008 (who knows what they did in 2007!) and brought their first product to market in 2010. Since then they have survived on product revenue.

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One Billion Transistor IC Layout Editing

One Billion Transistor IC Layout Editing
by Daniel Payne on 06-11-2012 at 6:33 pm
Categories: EDA

There are only a handful of billion transistor IC designs in existence today, so when an EDA company touts 1 trillion transistor IC layout editing then I take notice. This year at DAC I met with Katherine Hayes and Karen Mangum of Micro Magic to get an update on their IC layout tools. Continue reading “One Billion Transistor IC Layout Editing”

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From SPICE Netlist back to Schematics at DAC

From SPICE Netlist back to Schematics at DAC
by Daniel Payne on 06-11-2012 at 5:22 pm
Categories: EDA, Events
4 Comments

I first heard about SPICE Vision Pro when working at Mentor Graphics where we needed a way to visualize SPICE netlists and debug SPICE simulation results node by node on a design where we didn’t have the original schematics. Last Monday I met the engineers from Concept Engineering in their booth at DAC to get an update, Gerhard Angst is the CEO.


Continue reading “From SPICE Netlist back to Schematics at DAC”

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Cadence/TSMC 3D

Cadence/TSMC 3D
by Paul McLellan on 06-11-2012 at 5:16 pm
Categories: Cadence, EDA

Mark Twain remarked that everyone talks about the weather but nobody does anything about it. 3D ICs seems to be a bit like that. Over the last couple of years there have been lots of people talking about 3D but very little that has actually been manufactured. In addition to the weather, everyone talks about Xilinx’s 3D Virtex design because it is about the only one that is in manufacturing (it is so high end I hesitate to say it is “volume manufacturing”).

All of Cadence, Synopsys and Mentor have talked about some aspects of 3D in their toolsets. The challenge with 3D is that it affects everything from synthesis on down and if only a few tools have been updated it is like a ladder with missing rungs, hard to get from one end to the other of the design flow.

At DAC, Cadence announced a full suite of tools that they have been working on with TSMC to create what they are calling the CoWoS Design Ecosystem. I met with John Murphy and Samta Bansal to find out more. The first obvious question is CoWoS, what is that? It stands for chip-on-wafer-on-substrate (or sometimes on-silicon) and is TSMC’s name for their heterogeneous silicon interposer approach. Heterogeneous in the sense that all the die on the interposer do not need to be from the same semiconductor process.

As a test vehicle the designed and manufactured the first heterogeneous CoWoS module. There were 3 die: a 40nm memory, a 65nm GPS and a 28nm SoC, all put together on a 65nm silicon wafer. And it is yielding. Nobody is saying how much yet, but just as with the Xilinx part, one of the major reasons for doing this sort of design is to get the learning experience of what it takes to make an economic solution.

As a result there is now a path for 2.5D interposer-based technology through a Cadence (almost entirely) flow from implementation, to analysis, to verification and including DFT and test solutions.

The flow starts with a fairly standard implementation of the top die, obviously bumped rather than designed to be bonded out, but using standard RDL routing. Wafer test is developed (which is very important in 3D designs, lots of known-good-die get wasted when a bad die slips through wafer sort). Next the interposer is designed and routed. The interposer itself needs to be analyzed and then the whole system of interposer and die (and I’m guessing package) to check everything is correct, that IR drop is within tolerance and pulling all the test together for a package level test that can test everything

Above is the first module on the Cadence booth. They also had it on the TSMC booth — but with big signs saying no cameras or camera-phones. I think this probably just reflects different cultural attitudes to secrecy. Cadence has done several other 2.5D chips. Nobody is yet ready to announced but Cadence claim 8 testchips and 1 production chip.

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A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools

A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools
by Daniel Payne on 06-11-2012 at 4:07 pm
Categories: EDA, Siemens EDA
2 Comments

Linda Fosler, Tom Daspit and Mitch from Mentor Graphics met with me last Monday at DAC to provide an update on IC layout and circuit simulation tools. My notes follow:

Overview – Pyxis for Schematic and Layout, IC Station is re-branded as Pyxis. (Pyxis schematic is still Falcon, Ample language is still used.) Continue reading “A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools”