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Synopsys’ Strategic Advancement with PCIe 7.0: Early Access and Complete Solution for AI and Data Center Infrastructure

Synopsys’ Strategic Advancement with PCIe 7.0: Early Access and Complete Solution for AI and Data Center Infrastructure
by Kalar Rajendiran on 06-25-2024 at 6:00 am

(From NewsRelease)Synopsys PCIe 7.0 IP Solution Infographic

In the rapidly evolving world of high-performance computing (HPC) and artificial intelligence (AI), technological advancements must keep pace with increasing demands for speed, efficiency, and security. Synopsys recently announced the industry’s first complete PCIe 7.0 IP solution. This groundbreaking initiative addresses current demands and anticipates future needs, highlighting the importance of early access to advanced technology, the benefits of providing a complete solution, and Synopsys’ pivotal role in the industry. I had an opportunity to gain further insights around this announcement, from Manmeet Walia, Executive Director, Mixed-Signal PHY IP at Synopsys.

Meeting the Demands of Modern Data Centers

The demand for computational power in AI and HPC applications is growing at an unprecedented rate. Large language models require the processing of trillions of parameters in real-time. Synopsys’ PCIe 7.0 solution, with its doubled bandwidth of up to 512 GB/s bidirectional in a x16 configuration, is designed to meet these exacting requirements. Early access to this technology is crucial for hyperscalers and AI data centers to stay ahead of the curve, enabling them to handle larger datasets, faster processing, and more complex algorithms efficiently.

One of the standout features of Synopsys’ PCIe 7.0 solution is its support for linear direct drive optics. This technology eliminates the need for additional digital signal processing (DSP) chips within the optical modules, reducing power consumption and latency. By directly interfacing with optical components, Synopsys’ solution enhances signal integrity and performance, making it ideal for high-speed data transfer over longer distances.

PCIe 7.0 Over Cable and Optics

The ability to extend PCIe 7.0 connectivity beyond traditional confines is a significant advancement. Synopsys’ demonstrations of PCIe 7.0 over both cable and optics address different facets of data center interconnectivity. Here is a short video clip of a PCIe 7.x, PCIe 6.x and 224G Over Optics Synopsys Demo from OFC 2024 Conference. PCIe over cable enables efficient communication within a rack, traditionally dominated by Ethernet. On the other hand, PCIe over optics facilitates high-speed, low-latency connections between racks and across data centers, supporting distances of up to 2 kilometers. This versatility is crucial for hyperscalers and AI data centers that need to manage vast amounts of data across distributed systems efficiently.

The Imperative of Early Access and Complete Solutions

The pace of innovation in data centers and AI applications necessitates early access to cutting-edge technology. Synopsys is offering an early access program for its PCIe 7.0 IP solution, set to be available in early 2025. By engaging with early adopters, Synopsys enables leading companies to integrate the latest advancements into their designs ahead of the formal standard ratification, expected by the end of 2025. This early access allows for thorough testing, optimization, and customization, ensuring that when the technology becomes mainstream, it is robust, reliable, and ready for mass deployment.

Synopsys’ complete PCIe 7.0 IP solution integrates a controller, PHY, IDE security module, and verification IP, offering a turnkey solution that addresses every aspect of data transfer needs. This complete package simplifies the integration process for customers, ensuring seamless compatibility and optimal performance. By providing a fully integrated solution, Synopsys reduces risks associated with piecemeal implementations, such as compatibility issues and suboptimal performance.

Synopsys’ Leadership and Industry Influence

With over 20 years of experience in PCIe technology, Synopsys holds a strategic vantage position in the industry. The company has a seat on the PCI-SIG board, giving it a deep understanding of upcoming standards and allowing it to influence the direction of PCIe technology. This insight enables Synopsys to align its IP product development closely with industry needs and standards. Synopsys’ extensive track record, with over 500 wins in PCIe Gen 4 IP solution and nearly as many in PCIe Gen 5 IP solution, underscores the company’s expertise and leadership in the field.

The Significance of Synopsys’ Partner Ecosystem

Synopsys’ PCIe 7.0 solution is further strengthened by robust industry support. Leading companies such as Intel, Astera Labs, Enfabrica, Kandou, XConn, Rivos, Microchip and Samtec have endorsed Synopsys’ technology, recognizing its critical role in advancing AI and data center infrastructure. This highlights the broad industry support for PCIe 7.0 and underscores the collaborative effort required to meet the complex demands of modern computing environments.

Demonstrations at PCI-SIG Developers Conference

Synopsys showcased two significant demonstrations at the PCI-SIG Developers Conference on June 12 and June 13, 2024. The first demo featured Synopsys PCIe 7.0 PHY IP running at 128 Gb/s with OpenLight’s Photonic IC, illustrating the electrical-optical-electrical (E-O-E) TX to RX connection. The second demo demonstrated the PCIe 7.0 Controller IP successfully establishing a root complex to endpoint connection with FLIT transfer. These demonstrations highlight the technology’s capabilities and readiness for deployment, reinforcing Synopsys’ leadership position in the PCIe ecosystem.

Below is a photo of the Demo setup in June 2024, at the PCI-SIG Developers Conference

 

Below is the eye diagram capture from Synopsys PCIe 7.0 PHY IP supporting 128 GT/s with PAM-4 signaling; the IP enables 512 GB/s bidirectional data transfers with 16 lanes

Summary

Synopsys’ introduction of the industry’s first complete PCIe 7.0 IP solution marks a significant milestone in the evolution of data center technology. By offering early access to this advanced technology, providing a complete and integrated solution, and leveraging its extensive experience and industry position, Synopsys is setting a new standard for high-performance, low-latency, and secure data transfer. The inclusion of linear direct drive optics and support for both cable and optical interconnects further enhances the solution’s applicability, ensuring it meets the diverse needs of modern data centers and AI infrastructures. As the demand for computational capabilities continues to grow, Synopsys’ PCIe 7.0 solution is poised to play a pivotal role in shaping the future of data center technology, backed by strong ecosystem support.

To learn more, visit the Synopsys PCIe 7.0 solutions page.

Also Read:

Synopsys-AMD Webinar: Advancing 3DIC Design Through Next-Generation Solutions

Reduce Risk, Ensure Compliance: Hardware-Assisted Verification for Design Certification

What to Do with All that Data – AI-driven Analysis Can Help


Automotive Semiconductor Market Slowing

Automotive Semiconductor Market Slowing
by Bill Jewell on 06-24-2024 at 6:00 pm

Semiconductor Market Growth 2024

We at Semiconductor Intelligence estimate the automotive semiconductor market was $67 billion in 2023, up 12% from 2022. The top twelve suppliers accounted for over three-quarters of the market. Infineon Technologies was the largest automotive semiconductor supplier, at $9.2 billion or 13.7% of the market. NXP Semiconductors was second at 11.2% and STMicroelectronics was third at 10.6%. These top three companies accounted for over one-third of the market. For most of these companies, automotive is a significant part of their total revenues. Of the top six companies, the percentage of revenues from automotive ranged from 34% to 56%.

The automotive semiconductor industry has shown strong growth since 2021 as the industry bounced back from pandemic-related shortages. However, there are signs of a slowdown in the market. The quarterly automotive semiconductor revenue of the top three suppliers reflects this trend. Infineon reported strong growth through 2022 and early 2023 but peaked in 2Q 2023 and has been declining since. Though Infineon’s automotive revenue guidance for 2Q 2024 is for 5% quarter-to-quarter growth. NXP saw quarter-to-quarter revenue growth through 4Q 2023 but reported a 5% decline in 1Q 2024. NXP’s 1Q 2024 report cited continued inventory reductions and a soft overall automotive market in the first half of 2024. ST’s quarter-to-quarter revenue growth was strong in 2022 and 2023, averaging 7%. That growth ended in 1Q 2024 when ST reported a 23% decline in automotive revenue, citing a “deceleration phase”.

Motor vehicle production in 2023 was 93.5 million units, according to the International Organization of Motor Vehicle Manufacturers (OICA), up 10% from 2022. This was the strongest production growth since 26% in 2010 during the recovery from the great recession of 2008-2009. The 93.5 million vehicles in 2023 were still below the all-time high of 97.3 million vehicles in 2017. The industry experienced moderate declines in 2018 and 2019 before dropping 15.4% in 2020 due to pandemic related shutdowns. Yet it appears much of the pent-up demand for automobiles has been satisfied. S&P Global Mobility’s April 2024 forecast is for light vehicle production growth in the 0% to 2% range over the next three years. The mid-points of S&P’s forecast range are shown in the table below.

Despite the slowdown in vehicle production growth, the automotive semiconductor market growth is driven by increasing semiconductor content per vehicle. Two key drivers of the increases are electric vehicles (EVs) and driver-assist systems. EVs, which include battery-electric vehicles (BEVs) and plug-in hybrids (PHEVs), have a higher semiconductor content than other vehicles and thus drive automotive semiconductor market growth. EVs have been growing rapidly in the last few years. Autovista24 estimates EV sales grew 54% in 2022 and 35% in 2023. However, growth is expected to moderate to the 17% to 22% range over the next six years.

Driver-assist systems have also been a key driver of semiconductor content. The ultimate goal of driver-assist systems is self-driving cars, or fully autonomous driving. However self-driving cars are several years away from being commonplace. McKinsey & company has estimated by 2030, 12% of passenger vehicles sold will have fully autonomous driving technology installed (level 4 technology). By 2035, it could be 37%. S&P Global Mobility is more pessimistic, predicting only 6% of light vehicles sold in 2035 will have level 4 autonomous driving installed. Thus, the impact of self-driving cars on the semiconductor market will not likely be of major significance in the next few years.

The overall semiconductor market has been weak the last two years after strong pandemic recovery growth of 26% in 2021. According to WSTS, the semiconductor market only grew 3.3% in 2022 and declined 8.2% in 2023. WSTS’ May 2024 forecast was for strong growth of 16.0% in 2024 and 12.5% in 2025. As we stated in our March 2023 newsletter, automotive has been the lone bright spot in the semiconductor market in the last two years. IDC estimated the automotive semiconductor grew 17% in 2022 and 10% in 2023. IDC’s May 2004 forecast called for the growth of the automotive semiconductor market slow to the 5% to 7% range over the next three years.

The combination of slowing production of light vehicles, slower growth of EVs, and delayed deployment of autonomous-driving vehicles will reduce the growth rate of the automotive semiconductor market. The semiconductor industry can no longer count on automotive as a major driver in the next couple of years. However, other sectors are expected to drive growth. Artificial intelligence (AI) is growing rapidly, spurring growth in the computer sector. The memory market has recovered from weak demand and overcapacity. The smartphone market has turned positive in 2024 after declines in 2022 and 2023. Yet the major automotive semiconductor companies are heavily dependent on automotive for the majority or a major portion of their revenues. Thus, they are likely to lag semiconductor industry growth in the next few years.

Also Read:

2024 Starts Slow, But Primed for Growth

Electronics Turns Positive

Semiconductor CapEx Down in 2024


System VIPs are to PSS as Apps are to Formal

System VIPs are to PSS as Apps are to Formal
by Bernard Murphy on 06-24-2024 at 10:00 am

System VIP Libraries and Solutions

In the formal world the core technology is extremely powerful, and specialist users need full access to tackle difficult problems. But for many applications, teams prefer canned solutions built on the core technology yet scalable to non-experts. A similar dynamic appears to be playing out between System VIPs and PSS. PSS, the system level simulation standard, is an extremely powerful approach to define portable system level tests. Powerful but different from the more familiar UVM standard for lower-level testing, which can be a speed bump for adoption. Dave Kelf (CEO of Breker Systems) told me that his customers have been telling him that while they like Breker’s PSS tests, they are looking for more canned system VIP solutions, for example around coherency testing. Hence my observation in the title. PSS technologies are still essential as the core, but teams now want more scalability through complete out-of-the-box system VIP solutions for standard system verification needs. While still being able to develop their own specialized tests as needed.

What is a System VIP?

The intent is the same as for an interface IP (USB, etc) – a method to generate traffic to drive design testing, along with checkers and scoreboards to check and monitor interaction between the VIP and the design. However rather than checking protocol compliance, System VIP checks system level behaviors such as cache coherence and interoperability between cores/clusters and the rest of the system.

There are some other important differences. An interface IP acts as a proxy for a design block or an external source. System VIPs by their nature don’t have a design equivalent. They act instead as test overseers for their area of interest. A coherency system VIP is a good example. This will at minimum generate traffic for end-point memory requests on a coherent network, checking and monitoring some level of cache controller and directory behavior, and compliance with the coherence protocol (e.g. MOESI). They probably also should provide some kind of scoreboard to accumulate coverage stats against target objectives.

The basic minimum for System VIP

As a relatively new field, an obvious question is “what should such VIPs provide at minimum?” Breker has developed a top-10 list of requirements over and above the basic VIP expectations, which I find quite useful. I’ll start with a zeroth requirement, implied for their list yet fundamental in PSS implementations.

System level tests scale up very fast. Unit tests (for a mesh network say) may run on a simulator but larger tests demand emulation or prototyping together with a virtual interface for the testbench, then virtual models to run software loads and interfaces to interact with other simulation platforms such as a network traffic simulator. The bigger the design gets (e.g. multi-die) the more varied and distributed the simulation platform becomes, each aspect bringing its own constraints to the test flow. PSS is designed to scale across these diverse modeling systems which is one of the reasons System VIPs are built on PSS.

The first 5 must-have’s start with a no-brainer: targeting system level operational scenarios rather than functional components. Of course, you need a configurable model for the VIP, scalable between different system designs and allowing for reuse. The VIP should be built on a detailed understanding of the domain, in the coherence case all the possible options and protocols, abstracting away detailed implementation choices. It should be scalable from unit (system) tests up to multi-die systems and it should support portability between simulation platforms so if I can abstract some part of the DUT in a virtual model if I want, or use a more accurate RTL model running on an emulator. All still under control of the same System VIP.

Dave and Adnan Hamid (Executive President and CTO) see the next 5 must-haves as areas where Breker offers differentiation. One is the ability to intermix verification objectives, so you can combine coherency checking with power management variations for example. A second is the ability to run multiple scenarios concurrently for stress testing. A System VIP should have self-checking tests and a scoreboard because that’s the kind of complexity hiding users want to see in System VIP. Breker also argue that System VIPs should be user extensible. And they say that these tests should support firmware and UVM code components.

Possibly some more must-haves could be added, but this list looks like a good starting point.

The Breker System VIP portfolio

Cache System Coherency is an obvious VIP since Breker have been working in this domain for a long time. Arm SoCReady provides testing against the hardware sections of Arm’s SystemReady certification, verifying compliance against the system-level hardware requirements. RISC-V SoC Ready provides a similar service design based on RISC-V cores. RISC-V CoreAssurance is an interesting complement for teams building RISC-V cores, who want to get a general assurance that the core will be compliant with a RISC-V ready checkout without having to build a surrounding SoC – or rather many such SoCs to get better coverage.

Breker also provides System VIP class solutions in a number of other domains, listed in the graphic above. I didn’t talk about these with Dave and Adnan but I’m sure they would be happy to share more details. You can learn more HERE.

Also Read:

Qualitative Shift in RISC-V Targets Raises Verification Bar

Breker’s Maheen Hamid Believes Shared Vision Unifying Factor for Business Success

Scaling the RISC-V Verification Stack


Silicon Catalyst Ventures Launched With 8 Fundings

Silicon Catalyst Ventures Launched With 8 Fundings
by Daniel Nenni on 06-24-2024 at 6:00 am

SemiWiki SCV process

Silicon Catalyst Inc. is a unique incubator dedicated exclusively to the semiconductor industry. Founded in 2015, SCI provides a comprehensive ecosystem to support semiconductor startups. You can see the full list of available resources on the Silicon Catalyst website.

We recently covered the ground breaking Silicon Catalyst Arm Start-up Contest which resulted in the award of $400,000 Arm technology credit!

Today’s announcement launches Silicon Catalyst Ventures to support Semiconductor Startups deploying $10M to $20M for its first series and is focused on investing in early-stage entrepreneurial teams developing semiconductor-based innovations.

Official Press Release

The SC Ventures team is led by seasoned investment and technology experts, including the former CEO of UMC Dr. Shih-Wei Sun, in close collaboration with Silicon Catalyst. Dr Sun joined Silicon Catalyst as an advisor and investor, as well as a member of the Silicon Catalyst Angels Investment group for the past two years:

“Silicon Catalyst Ventures was formed as an extension of Silicon Catalyst, the world’s only incubator + accelerator focused on semiconductor solutions. It has been formed primarily, but not exclusively, to fund and foster Silicon Catalyst Portfolio Companies.,” stated Dr. Sun. “This close association between our fund and the Silicon Catalyst incubator affords investors unique access to startup teams whose technology and businesses are de-risked throughout a thorough and rigorous incubator screening process and then, when accepted, through Silicon Catalyst’s world-class two-year incubation. With our top-ranked semiconductor LPs, we bring additional ecosystem and supply-chain values to our startups. Silicon Catalyst Ventures is looking forward to tapping into the immense financial and societal value of our industry in this Silicon Renaissance era.”

Joining Dr. Sun and Pete Rodriguez (CEO of Silicon Catalyst) in the leadership team of Silicon Catalyst Ventures are:

Laura Swan – General Partner and Portfolio Manager
Laura oversees portfolio company management at SCV. Laura is a Managing Partner with Silicon Catalyst and the Vice President of Operations for Silicon Catalyst Angels.

Kai Chen – General Partner and Fund Manager
Kai oversees fund administration and investor relations at SCV. He is the founder and CEO of OceanIQ Capital, an investment advisory firm that he started in 2013.

Julian Lee – Managing Director
Mr. Lee has 35 years of professional experience in investment banking and the telecom/media industry.

One of the people joining Dr. Sun on the leadership team of Silicon Catalyst Ventures is new (to me) member Kai Chen.

Kai is the Founder and CEO of OceanIQ Capital, a boutique private wealth manager that manages portfolios for cross-border families. He was responsible for sourcing, evaluating, and executing investments in over 20 private equity, venture capital, and real estate funds as LPs, as well as over 30 venture-backed start-ups as SPVs. Kai oversees fund administration and investor relations at SCV. Kai Was brought in by Dr SW Sun to raise capital for the investments.

I spoke with Kai and asked what excites him most about the semiconductor industry. He said he did a study of the largest companies in the world and now more than half are semiconductors. In his view semiconductors are underinvested and acquisitions are just starting to ramp up so there is plenty of opportunity. The one concern he had, that I share, is that AI infrastructure is by far outspending AI revenue which may lead to a bubble at some point in time.

Here are the initial SCV investments from the Silicon Catalyst Incubator with more to come:
Silicon Catalyst Incubator Application Deadline

The deal flow for Silicon Catalyst Ventures is primarily sourced from companies that are admitted to the Silicon Catalyst Incubator. Early-stage semiconductor companies that are admitted to the Incubator will be eligible to receive an investment from Silicon Catalyst Ventures.

The application deadline for Silicon Catalyst is July 12, 2024; details can be found at https://siliconcatalyst.com/application

If you are a startup and interested in applying for funding, please apply through the Silicon Catalyst Incubator – www.sicatalyst.com

If you are interested in becoming a Limited Partner, contact laura@sicatalystvc.com.

Also Read:

Silicon Catalyst Announces Winners of the 2024 Arm Startups Contest

A Webinar with Silicon Catalyst, ST Microelectronics and an Exciting MEMS Development Contest

Silicon Catalyst partners with Arm to launch the Arm Flexible Access for Startups Contest!


Podcast EP229: A Detailed Look at the DAC Engineering Track with Ambar Sarkar

Podcast EP229: A Detailed Look at the DAC Engineering Track with Ambar Sarkar
by Daniel Nenni on 06-21-2024 at 6:00 pm

Dan is joined by Dr. Ambar Sarkar, a member of the Design Automation Conference executive committee and the program chair of the Engineering Tracks. He has a broad background covering both software and hardware R&D. He has contributed to industry standards in areas such as functional verification and IP security. He is the IEEE Computer Society’s representative for IEEE USA’s AI and Autonomous Policy Committee. Ambar is an individual contributor at NVIDIA where he enjoys working on compute and storage resource optimizations across large engineering teams. He is now also exploring the area of generative AI.

Ambar explains the focus and composition of the engineering track program at DAC. This part of the conference is focused on practical considerations for advanced product innovation. It is a peer-to-peer event where practicing engineers can exchange results and ideas. Topics covered include front-end design, back-end design, IP and software development.

Ambar also explains the extensive peer review processes behind both submitted and curated content for DAC. He discusses the many special events that will occur during DAC, including the popular poster gladiator competition that uses a live panel of judges and audience to determine the best poster presentation. He also covers the impact AI is having on chip design.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Daniel Nenni at the 2024 Design Automation Conference

Daniel Nenni at the 2024 Design Automation Conference
by Daniel Nenni on 06-21-2024 at 4:00 pm

DAC 2024 Banner

This year’s live semiconductor ecosystem conferences have been well attend and I expect the same for #61DAC next week. I will be at the conference from Sunday afternoon to Wednesday evening, if you would like to meet let me know. Networking is an important part of the semiconductor ecosystem so let’s make it happen.

The final opportunity to meet me at #61DAC will be on Wednesday afternoon. I will be moderating a panel on 3DIC, one of the more popular topics on SemiWiki.

Research Panel, Wednesday, June 26 @ 3:30pm – 5:30pm PDT, 3014, 3rd Floor
3DIC Design Ecosystem – The Cats That Need Herding!

At the end of 2D scaling of Moore’s law, 3D integrated circuits that take advantage of advanced packaging and heterogeneous integration offers many prospects of extending the chip density scaling and the system performance improvements for the next decade. Much of 3DIC design activity in the industry today is done via different teams within the same company. 3DICs hold the potential to not only make the chip architecture heterogeneous, but also chiplet sourcing to be highly diversified. Moreover, 3DICs themselves have a few avenues to be realized towards commercial success, ranging from true disaggregated chiplets to sequential stacked processing. This presses us to answer a few key questions:

1. Technology:

a. How will heat dissipation be managed, are new cooling techniques being pursued to mitigate the thermal challenges?

b. How to design the power delivery network from the board to the substrate to the multi-tier of 3D stack with minimal voltage drop and high-power conversion efficiency? How to design the backside power delivery in leading edge node CMOS with 3D stacking?

c. How to ensure signal integrity, yield and reliability between multiple tiers of 3D stacking, and what testing and standardization efforts are needed to embrace the heterogeneous dies from different designers and different foundries?

2. EDA flows and interoperability

a. Will the ecosystem extend the same standards-based interoperability of design tools, flows and methodologies to 3DIC, as enjoyed by system designers today?

b. How can the EDA industry help system designers in planning, managing and tracking their complex 3DIC projects in implementation, analysis, and signoffs?

3. Roadmap:

a. Is the roadmap to sequential monolithic stacked 3DIC inevitable? What factors will lead the industry to it?

b. What are the boundaries between monolithic 3D integration (with sequential processing at BEOL) and heterogenous 3D integration (with die stacking or bonding)?

We as an industry must be able to apply lessons from the past struggles with monolithic chip design and interoperability to this emerging challenge. This panel will discuss the need, scope of solution, and potential candidate efforts already in motion.

I hope to see you there!

Also Read:

Breker Verification Systems at the 2024 Design Automation Conference

Flex Logix at the 2024 Design Automation Conference

Alphacore at the 2024 Design Automation Conference


Breker Verification Systems at the 2024 Design Automation Conference

Breker Verification Systems at the 2024 Design Automation Conference
by Daniel Nenni on 06-21-2024 at 2:00 pm

DAC 2024 Banner

Breker Verification Systems will demonstrate its new RISC-V CoreAssurance™ and SoCReady™ SystemVIP™ along with its Trek Test Suite Synthesis portfolio during the 61st Design Automation Conference (DAC) in Booth #2447. DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

RISC-V cores require an extensive amount of verification, including capabilities uncommon in general block verification, required to achieve the quality bar set by Arm and X86. RISC-V processor core verification can be considered as a stack of verification tests starting with basic operational tests, ISA compatibility and micro-architectural testing, then leading to integrity and integration testing to ensure system level compatibility, and performance testing.

Breker’s RISC-V CoreAssurance SystemVIP provides the complete range of tests for the entire RISC-V core verification stack. Starting with randomized instruction generation and microarchitectural scenarios, SystemVIP includes tests that check all integrity levels ensuring the smooth application of the core into an SoC, regardless of architecture, and the evaluation of possible performance and power bottlenecks and functional issues.

It can be extended for custom RISC-V instructions to be incorporated into the complete test suite crossed with other tests. It is self-checking and incorporates debug and coverage analysis solutions and can be ported across simulation, emulation, prototyping, post-silicon and virtual platform environments.

The Breker SoCReady SystemVIP extends these capabilities for teams integrating RISC-V processors on SoCs needing to ensure SoC issues such as load store efficiency, interrupt testing, coherency, security and more are fully evaluated. It is also useful to ensure the quality of RISC-V cores obtained from other vendors.

Based on synthesis technology, the SystemVIP amplifies scenario models to improve coverage and bug hunting. An AI technique called Planning Algorithms explores the state space of the various scenarios starting with the desired end space and working backward to initial inputs. This technique allows for precise test execution that tracks from input to specific states leading to more effective bug hunting with fewer tests than a more general hit and miss randomized approach.

Test cross combination is another synthesis technique that combines various scenario components in a multi-dimensional series of tests. For example, crossing different privilege levels with branch prediction and load store scenarios to build combined tests grows the odds of an unusual corner case issue occurring.

Scheduling concurrent scenarios further increases pressure on design components to reveal difficult bottlenecks in design architecture by “torturing” the device to reveal weaknesses. Tests are scheduled together across HARTS and multicore processors that overload SoC resources, allowing the performance of the tests to be examined in a profiling window.

Breker’s SystemVIPs are used for a variety of complex RISC-V core designs, including system coherency in a multicore SoC. integrity test sets, high-coverage core test, power domain switching, hardware security access rules and automated packet generation

Breker’s RISC-V CoreAssurance and SoCReady SystemVIPs are available now as are its Test Suite Synthesis solutions. Pricing is available upon request. For more information, visit the Breker website or email info@brekersystems.com. To arrange a demonstration or private meeting at DAC, send email to info@brekersystems.com.

DAC registration is open.

Also Read:

OPENEDGES Technology at the 2024 Design Automation Conference

Weebit Nano at the 2024 Design Automation Conference

Agnisys at the 2024 Design Automation Conference


Flex Logix at the 2024 Design Automation Conference

Flex Logix at the 2024 Design Automation Conference
by Daniel Nenni on 06-21-2024 at 12:00 pm

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The rapid technological evolution and soaring mask set costs have created numerous challenges for designers today. Protocols, algorithms, and cryptography are all advancing at a blistering pace, leaving designers struggling to keep up. While fab suppliers are enhancing performance and reducing power consumption, this progress comes at a price – limiting the number of affordable mask iterations for manufacturers. Flex Logix provides a compelling solution, offering hardware acceleration and reconfigurability that can save designers time and money, arriving at the perfect moment.

Flex Logix’s embedded FPGA IP, EFLX, is highly optimized for SoC and ASIC implementation, providing the performance and functionality of traditional off-the-shelf FPGAs. The scalable EFLX IP ranges from 200 to over 1 million logic cells, enabling IC designers the flexibility to adapt to evolving interfaces, protocols, and algorithms. Furthermore, production products can use this IP to repair bug fixes, provide lasting security, and meet unique regional requirements without costly design respin. Adding eFPGA IP offers additional value by enabling different functions at various stages of the product lifecycle. During IC bring-up, the IP can facilitate built-in self-testing and debugging. In production, the IP can multitask as a cryptographic controller, algorithm accelerator, interface expander, or other desired function.

Flex Logix offers signal processing IP, InferX, which can dramatically accelerate DSP and AI algorithms. Many designers use FPGAs for signal processing due to their abundance of multipliers and localized memory. Flex Logix takes this a step further by enabling advanced mathematical functions like matrix inversions, filters, and transforms in InferX. This IP can achieve exceptional performance at incredibly low power and area. Its scalable AI inference is highly efficient, delivering much higher inference throughput per square millimeter and per watt. Interested parties can visit Flex Logix’s booth to see a live demo of this innovative technology.

We are also thrilled to launch our new eXpreso FPGA Compiler – a powerful upgrade to our EC1 compiler. This cutting-edge tool boosts designer productivity with up to 10x faster compilation, 50% better performance, and 2x logic area reduction. We will also be demonstrating this at our booth, stop by to see how efficiently this tool can implement complex algorithms.

Flex Logix is a leading provider of reconfigurable computing technologies, including its innovative eFPGA and AI Inference solutions for semiconductor and systems companies. Flex Logix’s EFLX eFPGA enables FPGA users to seamlessly integrate the FPGA into their companion SoCs, resulting in a 5-10x reduction in the cost and power of the FPGA while increasing compute density – a critical advantage for applications in communications, networking, data centers, microcontrollers, and more. Flex Logix’s IP integrates seamlessly into any SoC or ASIC, and with over 100 US patents and applications, it offers top-tier power, performance, and area (PPA) metrics, compatible with cutting-edge nodes like Intel 18A, TSMC 7nm, and 5nm. The scalability of Flex Logix’s eFPGA IP empowers users to optimize their resources for enhanced flexibility.

Interested in Flex Logix IP? Visit our website at https://flex-logix.com email us at info@flex-logix.com.  We’d love to meet you at the Design Automation Conference in San Francisco from June 24-26 at booth #1327, where we can discuss the many use cases and benefits of our IP.

Also Read:

Elevating Your SoC for Reconfigurable Computing – EFLX® eFPGA and InferX™ DSP and AI

Reconfigurable DSP and AI IP arrives in next-gen InferX

eFPGA goes back to basics for low-power programmable logic


Alphacore at the 2024 Design Automation Conference

Alphacore at the 2024 Design Automation Conference
by Daniel Nenni on 06-21-2024 at 10:00 am

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Alphacore Inc., an industry leader in proven high-performance analog and radio-frequency (RF) design building blocks, end products, and intellectual property (IP) licensing and non-recurring engineering (NRE) design services. Our customers include multi-national corporations to ground-breaking startups. We were founded in 2012 with headquarters in Arizona’s center of technological innovation, the Silicon Desert. Our engineering and leadership team combines long histories of delivering innovative data converter, RF, analog and mixed signal products, and complete imaging solutions for critical systems, through their business success at both startups and multinational companies.

We drive next-generation ultra-high speed, ultra-low power, radiation tolerant validated data conversion technology with IP designs enabling applications such as 5G/6G Communications, Beam Forming, Automotive sensing, Aerospace and Defense.

At Alphacore, our customers appreciate the specialized Design Services we offer for high performance/low power integrated circuit intellectual property (IP), Analog/Mixed Signal, harsh environments/robustness where our knowledgeable designers create novel analog building blocks and complete circuits using established and leading-edge process technology nodes for demanding conventional and harsh-environment applications.

Our designs utilize advanced technologies from broad-based suppliers such as TSMC and GlobalFoundries, as well as multiple specialty foundries, based on customer requirements and best fit for the application. Alphacore is a proud member of the GlobalFoundries® (GF®) FDXTM Network.

Visit our website (www.AlphacoreInc.com) to view our ever-growing  portfolio of IP solutions, including a wide range of megasample and gigasample per second (MS/s and GS/s) ADC and DAC IP products (e.g., 11-bit, 5 GS/s ADC A11B5G;  6-bit, 5 GS/s DAC D6B6G).

We specialize in designing high performance solutions for the niche needs of demanding market segments that address harsh environments, including scientific research, aerospace, defense, medical imaging, and homeland security. Accordingly, our engineering team includes seasoned device physics and “Radiation-Hardened-By-Design” (RHBD) experts.

At Alphacore, we offer products that focus on delivering uncompromised world-class performance while also meeting strict size, weight, power, cost (SWaP-C), and environmental constraints. Our customers get the best of both worlds.

Strategic core business areas include:
  • High performance and low power analog, mixed signal, and RF electronics
  • High-speed visible light and infrared Readout ICs (ROICs) and full camera systems
  • Robust Power Management ICs (PMICs) for space and high-energy physics experiments
  • Innovative devices ensuring supply chain and IoT cybersecurity

Our customers benefit from prioritized focus on their projects, keen attention to detail, and a higher level of care and responsiveness that we deliver. It is crucial for us to ensure the complete satisfaction of our customers, both in our products and in the way we do business. That is why we work with companies to create adaptable plans of action, and provide flexibility in our commercial contracts and agreements. We adhere to International Traffic in Arms Regulations (ITAR) and maintain Cybersecurity Maturity Model Certification (CMMC) compliance.

Alphacore is a regular participant supporting this industry-leading event, and we invite you to meet with our Alphacore experts on the exhibit floor. You can contact Alphacore here to schedule a meeting at booth #2332. We hope to see you there!

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Pragmatic at the 2024 Design Automation Conference

Pragmatic at the 2024 Design Automation Conference
by Daniel Nenni on 06-21-2024 at 8:00 am

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Pragmatic is pioneering a fundamental shift in semiconductor technology, delivering lower-cost, lower-carbon intelligence to power the Internet of Everything. Its FlexIC – flexible integrated circuit – technology delivers connect, sense and compute capabilities at a fraction of the cost and carbon footprint of silicon chips.

The FlexIC Foundry® enables rapid, high-volume fabrication with a high level of customisation, taking designs from tape-out to delivery in just weeks. The unique, low-temperature processes consume less energy and water, with fewer harmful chemicals, making Pragmatic one of the most sustainable semiconductor manufacturers in the world.

This year, Pragmatic Semiconductor will be setting up stall at the Design Automation Conference (DAC) for the first time.

Visit stand 1534 to discover their new, industry-standard 300mm wafers, as well as demos including:

  • PlasticARM
    The groundbreaking ultra-minimalist Cortex-M0-based SoC boasting 128 bytes of RAM and 456 bytes of ROM – 12x more complex than previous state-of-the-art flexible electronics
  • Electronic nose
    The world’s first machine-learning-based flexible mixed-signal chip, integrated with a flexible electronic nose sensor array.
  • Temperature sensors
    A selection of Flex-IC based sensors in a thin, flexible form factor:

    • Standalone temperature sensor
      A discrete linear PTC temperature sensor, supporting a wide operating window
    • I2C temperature sensor
      Integrated analogue front-end and digital I2C temperature readout, enabling wide-array sense capability
    • Temperature sensor with heating element and control logic
      Fully integrated heater FlexIC with on-chip sensor, control logic and heating elements
  • NFC products
    For applications including consumer engagement, authentication and tamper detection
About Pragmatic

Pragmatic has developed an integrated circuit (electronic ‘chip’) platform that doesn’t rely on silicon. Our revolutionary technology uses thin-film semiconductors to create flexible integrated circuits that are thinner than a human hair and are significantly cheaper and faster to produce than silicon chips. This provides a compelling alternative for many mainstream electronics applications, as well as enabling new applications not possible with silicon.

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