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Semiconductor Expert Forum

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Siemens Hardware-Assisted Verification at the 2024 Design Automation Conference

Siemens Hardware-Assisted Verification at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 8:00 am
Categories: EDA, Events, Siemens EDA

DAC 2024 Banner

Visitors to Siemens’ booth (#2521) at the 61st Design Automation Conference (DAC) will see on display the Veloce™ CS system that unifies hardware emulation, enterprise prototyping and software prototyping into one hardware-assisted verification and validation platform.

The display will feature the three single-blade system designed for engineering teams to add scalability and capacity as needed: Veloce Strato CS for emulation, Veloce Primo CS for enterprise prototyping, and Veloce proFPGA CS for software prototyping.

The evolution of SoC and system level design made the use of hardware-assisted verification a necessity, an opportunity Siemens embraced. It worked with key customers and partners to develop Veloce CS’ new, fully unified software architecture and innovative hardware built on two highly advanced ICs –– Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC for enterprise and software prototyping.

Architected for congruency, speed, and modularity across all three platforms, the Veloce CS system supports design sizes from 40 million gates up to designs integrating more than 40+ billion gates. Veloce CS executes full system workloads with superior visibility and congruency by selecting the right tool for the task, as each task has unique requirements. The result is faster time to project completion and assists in decreasing cost per verification cycle.

Veloce CS system addresses the specific needs of hardware, software and system engineers who play an essential part in delivering the world’s most advanced electronic products by providing the right tool for the task:

  • Veloce Strato CS delivers significant emulation performance improvement over Veloce Strato, up to 5x maintaining full visibility and it scales from 40 million gates (MG) to 40+ billion gates (BG).
  • Veloce Primo CS, based on AMD’s latest Versal Premium VP1902 FPGA, a congruent enterprise prototyping system that scales from 40MG to 40+BG.

Both the Veloce Strato CS and Veloce Primo CS solutions run on the same operating system for congruency while providing the freedom to seamlessly move between platforms. This can dramatically accelerate ramp up, setup time, debug, and workload execution.

  • Veloce proFPGA CS also leverages the AMD Versal Premium VP1902 FPGA-based adaptive SoC, which delivers a fast and comprehensive software prototyping solution, scaling from one FPGA to hundreds. This performance, together with its flexible and modular design, can help engineers accelerate firmware, operating system, application development and system integration tasks.

The entire Veloce CS system is available in a modular blade configuration fully compliant with modern datacenter requirements for easy installation, low power, superior cooling, and compact footprints. Further, the Veloce proFPGA CS solution provides a desktop lab version for additional user flexibility.

General availability of the three hardware platforms is planned for < >2024. Pricing is available upon request. For more information, visit the Siemens website. To arrange a demonstration or private meeting at DAC, send email to

DAC registration is open.

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Verific at the 2024 Design Automation Conference

Verific at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 6:00 am
Categories: EDA, Events, Verific

DAC 2024 Banner

Verific Design Automation will host two well-funded AI EDA startups and latest users of Verific’s front-end platform in its Design Automation Conference (DAC) booth, affirming its position as the leading provider of front-end platforms powering an emerging market.

Primis.ai and Silimate, both founded by former chip designers, will be in the Verific AI showcase in booth #1414 presenting their unique use of AI technology to eliminate error-prone repetitive tasks for efficient and more productive chip design. They employ Verific’s unsurpassed language support for fast, accurate LLM development, speeding time to market for products that range from functional verification, chip design to code development.

PrimisAI offers a generative AI solution for chip design with advanced language-to-code and language-to-verification capabilities through its interactive AI assistant to address complex hardware challenges across the entire design stack from concept to bitstream/GDSII. RapidGPT, unveiled earlier this year, lets engineers interact with their design and the entire EDA ecosystem with a natural language interface, boosting productivity and accelerating time-to-market. Founded by serial entrepreneur Naveed Sherwani who serves as chairman and CEO, Primis.ai is backed by two early-stage investors.

Silimate, backed by Y Combinator, is building the co-pilot for chip designers to help build better chips faster. Silimate finds functional bugs, predicts power, performance and area (PPA) issues, and recommends real and accurate fixes in real time, and is already being used by chip teams building complex IP and SoCs. Co-founders Ann Wu and Akash Levy previously built chips and EDA tools at Apple, Stanford, NVIDIA, and Synopsys.

Metalware, co-founded by Ryan Chow and Andrew Nedea, is also an AI EDA startup employing Verific’s front-end parser platforms. With initial funding from Y Combinator, Metalware has the mission to accelerate embedded development using AI technology after personally experiencing repeated bottlenecks in embedded software at SpaceX. The Metalware AI EDA tools help designers rapidly write HDL and embedded C/C++ by combining insights from manuals, datasheets and code, offering 10x faster development by automating low-level programming.

Another AI EDA startup in stealth mode is also a new Verific customer that will be announced shortly.

PrimisAI and Silimate will be in the Verific DAC Booth #1414 at various times of the day to give 10-minute presentations. Stop by the booth for a listing of times.

Verific will also demonstrate the latest releases of its SystemVerilog, Verilog, VHDL and UPF front-end parser platforms.

Of course, this year’s giveaway will be the Verific Giraffe. Stop by to get one. To arrange a demonstration or private meeting, send email to info@verific.com

DAC registration is open.

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SmartDV at the 2024 Design Automation Conference

SmartDV at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 8:00 pm
Categories: EDA, Events

DAC 2024 Banner

SmartDV’s presence at 61st DAC centers on connections, support, and the human side of IP. Over the past 18 months, we have been laser-focused on focused on overhauling and streamlining our customer support model to provide our global IP users with the best possible service. Vice President of Application Engineering Sergio Marchese has redoubled his AE team’s efforts to ensure that each user has the experience of a true partnership around their design success. This includes both customer-facing and internal improvements, such as:

  • Implementation of a customer success portal for improved ticketing, tracking, and responsiveness
  • Refinement of the product delivery process and related specification documents
  • Overhaul of the AE onboarding process to afford new members of our team a smoother, more efficient, and thoroughly supported path to getting up to speed and becoming successful in their roles
  • Strengthened lines of communication with our R&D team

We recently received the following generous feedback from longtime VIP user Ricoh, via a manager in their development department: “SmartDV’s strength lies in the individualized customization of VIP and the speed of their support. SmartDV has been flexible in responding to our requests for additional features and improving the readability of our development manuals. This is what differentiates SmartDV from other VIP vendors.”

We strive to offer exceptional support to each of our IP users, and ensuring that we hit the mark is our top priority. We can only achieve this goal through building strong relationships with our customers, taking on board their feedback, learning from our missteps, and challenging ourselves to consistently improve our processes. We’d love the opportunity to work with, and learn from, you and your team!

Whether you’re designing SoCs, ASICs, or FPGAs, SmartDV has design IP and VIP to suit your needs in the following categories:

  • Controllers, Peripherals, and Interface IP
  • Simulation VIP
  • Emulation/FPGA Transactor VIP
  • Formal Assertion VIP
  • Post-Silicon Validation VIP

We invite all IP enthusiasts to stop by our DAC booth (#2429) to share what you’re planning for your next chip design. We’d love the chance to investigate how we can be of service with our broad portfolio of design IP and VIP—and our ability to customize our offerings to meet your unique design needs. To give a nod to relationships and the human connection, you’ll have the chance to customize your own LEGO Minifig to look like yourself or anyone else of your choosing as you select hair, facial features, and other unique components. We’ll also have a giant LEGO wall where you can leave your mark as you chat with our team about upcoming design projects.

At SmartDV, we look forward to building things with you—at DAC and beyond.

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Blue Pearl Software at the 2024 Design Automation Conference

Blue Pearl Software at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 6:00 pm
Categories: EDA, Events

DAC 2024 Banner

Twenty years ago, Blue Pearl showcased its first-generation ASIC and FPGA static verification solution at the 2004 Design Automation Conference. If you are attending DAC 2024, stop by booth 1439 and see how 20 years of product development on the Visual Verification Suite has made chip design much more efficient.

The Visual Verification Suite offers project level verification as you code, for ASIC, FPGA, and IP RTL with advanced RTL structural and formal linting and constraint generation. An optional integrated low-cost glitch, clock and reset domain crossing analysis package, complete with our Advanced Clock Environment providing visualization of clock domains to help designers set up and analyze designs for CDC/RDC caused metastability. The suite’s usability for bug hunting and fixing is proven to help design teams accelerate development while ensuring high reliability designs.

In addition, the suite’s Management Dashboard provides progress reports for audits and design reviews ensuring that all tests have been completed and passed prior to tape out and signoff.

What’s special with our latest release is that we have been partnering with Accellera to develop a standard format to capture CDC/RDC/Glitch intent and have our initial release with the new standard.

The challenge we are addressing is design teams cannot reuse IP-level CDC collateral in their environments if both teams use different CDC verification tools. This scenario is causing a CDC verification problem when the development teams source IP from IP providers that use a different tool for their own CDC verification. To perform holistic top-level verification, additional resources are needed to reconverge the IP with the verification tool used by the other team. Redoing IP-level CDC verification is time consuming and labor intensive.

The Accellera CDC working group’s objective is to develop a standard format to capture CDC/RDC/Glitch intent. This will enable interoperability of CDC collateral generated by different CDC verification tools. The working group is focused on the effort to produce a formal Language Reference Manual. Blue Pearl is actively engaged and adding new features to support this endeavor.

In addition, as an EDA tool provider that tailors to military, aerospace, medical, communications and safety critical design companies our Visual Verification Suite now supports Lattice and EFINIX FPGAs as well as AMD, Intel/Altera, Microchip and NanoXplore SAS FPGAs.

Finally, Adam Taylor a world recognized expert in design and development of embedded s system and FPGA’s , as well as CEO of Adiuvo Engineering and Training will in the BPS booth talking about his use of the Visual Verification Suite and the benefits to his team’s development efforts.

You can contact Blue Pearl here to schedule a meeting at booth #1439 or just stop by. We hope to see you there!

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Cycuity at the 2024 Design Automation Conference

Cycuity at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 2:00 pm
Categories: Cycuity, Events, Security

DAC 2024 Banner

Cycuity is looking forward to showcasing the latest updates and new capabilities of its Radix security technology at their booth this year, once again located near the DAC Pavilion. Radix offers a systematic and robust approach to hardware security verification, helping organizations identify and address security weaknesses early in the chip design lifecycle.

Cycuity’s security solutions accelerate detection of security weaknesses and deliver comprehensive security assurance through scalable, repeatable and traceable security verification from the beginning of chip design to delivery. The company’s proven methodology ensures security by design through a unique approach rooted in hardware security expertise.

With Radix, defining clear and measurable security requirements becomes a seamless process. This capability is crucial for creating a strong security foundation that can be monitored and verified systematically throughout the design process. Radix does this by simplifying the creation of security rules and ensures these rules are consistently applied and validated across chip design.

Radix’st in-depth security analysis capabilities enable visualization and exploration of every aspect of a chips’ design, providing unique insights into previously unknown or unexpected behaviors, allowing users to pinpoint security weaknesses and strengthen security measures.

Radix’s patented information flow technology tracks information about critical assets and attack surfaces throughout design at all times to identify weaknesses that could otherwise go undetected. Additionally, Radix’s security analytics quantify and verify the completeness of security test coverage, ensuring existing security measures are both effective and comprehensive, making it easier to demonstrate security rigor to customers and regulations.

Semiconductor security continues to be a growing and urgent focus across both commercial and government sectors, and Cycuity CEO, Andreas Kuehlmann, will be joining other industry security experts in the Advancing Chip Security to Meet Heightened Requirements panel discussion on Tuesday, June 25.  The panel will delve into how emerging standards and a growing threat landscape  are driving the necessity for enhanced cybersecurity measures across all industries.  Stop by to meet team Cycuity in Booth 2351 before or after the panel session.

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RAAAM Memory Technologies ay the 2024 Design Automation Conference

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RAAAM Memory Technologies ay the 2024 Design Automation Conference

RAAAM Memory Technologies ay the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 12:00 pm
Categories: Events, IP

DAC 2024 Banner

This is the first year that RAAAM is attending DAC and presenting its revolutionary on-chip memory technology. Remember, DAC is the #1 EDA networking event where new technologies are often launched and this is one of many examples for #DAC2024.

Modern chips in various applications, such as Artificial Intelligence (AI) and Machine Learning (ML), Augmented / Virtual Reality (AR/VR), Automotive, 5G, High performance compute in data centres, etc., require ever-growing amounts of on-chip memory (SRAM) to meet the necessary performances under AI workloads. As a result, the amount of SRAM on almost any chip accounts for over 50% of the chip size. Furthermore, Moore’s Law has ended for SRAM, which no longer scales in advanced CMOS process nodes, resulting in limited on-chip memory capacities and significant cost increase for fabrication.

RAAAM’s GCRAM is the most cost-effective on-chip memory technology in the semiconductor industry, providing up-to 50% silicon area reduction and up-to 10X reduced power consumption over SRAM, and it is fully compatible with the standard CMOS fabrication flow, requiring no additional process steps or cost. RAAAM’s patented technology, an outcome of over a decade of R&D efforts, enables the extension of Moore’s Law for on-chip memories and can be used by semiconductor companies as a drop-in replacement for SRAM in their chips.

RAAAM’s GCRAM will allow customers to significantly reduce their chip cost and power consumption, or alternatively double the on-chip memory capacity with no extra cost, significantly reducing 1000X more the power-consumed due to off-chip memory accesses.

RAAAM’s GCRAM was implemented in various process nodes of leading foundries and full technology qualification is performed based on customers’ demand. 5nm and 16nm solutions are in the commercialization phase and migration to additional process technologies will be implemented during 2025.

RAAAM is one of the many companies participating in this industry-leading event, and you are invited to meet our team on the exhibit floor. We look forward to explore how GCRAM technology can help your product. Please contact RAAAM Here to schedule a meeting at booth #1460. I hope to see you there!

About DAC

DAC is recognized as the global event for chips to systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE) and is supported by ACM’s Special Interest Group on Design Automation (SIGDA) and IEEE’s Council on Electronic Design Automation (CEDA).

About RAAAM Memory Technologies

RAAAM has developed the most cost-effective on-chip memory technology in the semiconductor industry, providing 50% area reduction over high-density SRAM and reduced power consumption by a factor of five. RAAAM’s patented technology can be used by semiconductor companies as a drop-in replacement for SRAM in their SoCs and can be manufactured cost efficiently using the standard CMOS process allowing to significantly reduce the die size. Founded in 2021, the company is headquartered in Israel with R&D center in Switzerland.

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Primarius Technologies at the 2024 Design Automation Conference

Primarius Technologies at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 10:00 am
Categories: EDA, Events, Primarius

DAC 2024 Banner

DAC attendees who stop by the Primarius Technologies booth (#1415) will be greeted by the breadth of its product portfolio that meet time-to-market windows and optimize designs for better yield, power, performance and area.

That includes ESDiTM, a chip-level human body model (HBM) analysis platform and PTMTM, a power device design and layout verification tool family, from Primarius’ acquisition of Magwel N.V., provider of 3D solver- and simulation-based layout analysis and design solutions for digital, analog/mixed-signal, power management, automotive and RF ICs.

Demonstrations will highlight Primarius’ fast, accurate modeling and cell library characterization and circuit simulation solutions based on its continuous innovation and R&D expertise, including:

  • SDEPTM, the spec-driven extraction platform that builds auto model extraction flows for fast SPICE model extraction, an engine enabling efficient Design-Technology Co-Optimization (DTCO), and an extended capability on top of the de facto golden-standard SPICE modeling platform, BSIMProPlusTM.
  • NanoSpice XTM, the latest high-performance SPICE simulator addressing simulation capacity and accuracy challenges of big post-layout designs at advanced process nodes.
  • NanoSpice Pro XTM, the latest FastSPICE simulator with simulation performance and accuracy needs tailored for SRAM, DRAM, Flash and big analog-on-top designs in high-performance computing, mobile, AI and other advanced applications.
  • NanoCellTM, the latest standard cell library characterization solution employs advanced distributed parallel architecture technology and cell circuit analysis extraction algorithms, embedded with a high-precision SPICE simulator.
  • ESDi, state-of-the-art HBM analysis, simulation and verification tool for on-chip ESD protection.

Chip companies worldwide rely on Primarius’ product portfolio as the continuous iteration of IC industry technology and complexity of IC manufacturing processes rise exponentially and challenges in designing and manufacturing high-end chips increase. Foundries and IDMs use Primarius tools and services to provide their design customers with more accurate SPICE models, completer and more reliable PDKs, and more comprehensive standard cell library within shorter development cycles. Chip designers who require stronger COT capabilities with customized devices and models, and re-characterized cell libraries based on actual applications benefit as well from Primarius’ products.

Primarius’ product portfolio is data-driven, achieving software and hardware synergy through leading semiconductor characteristic testing instruments and EDA products. It provides device testing systems for a full range of device characteristics such as IV, CV, reliability, statistical variation, and the industry-golden low frequency noise testing systems, 9812 series, used by semiconductor companies worldwide. Its latest release, 9812AC, is the only commercial low-frequency noise system under AC excitation, designed for the most advanced process development and chip designs.

Primarius provides complete EDA toolchain and a one-stop design enablement technical development solutions. Innovations like these can shorten the SPICE model development cycle from several months to a few weeks or even hours for quick iteration, addressing the efficiency bottleneck of DTCO. The advanced simulation technologies speed-up challenging circuit simulation, and the latest cell library characterization solution provides throughput with near-linear scaling on thousands of x86 or ARM CPU cores on computer farm or public cloud.

It enables faster turnaround from technology development to advanced chip designs, and solutions include advanced analysis capabilities for high-sigma yield, aging, EM/IR, ESD and signal integrity, targeting optimum yield and PPA.

Primarius Technologies will be in DAC booth #1415.

To arrange a meeting or demonstration of the Primarius Technologies product portfolio, send email to: contact@primarius-tech.com.

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Agnisys at the 2024 Design Automation Conference

Agnisys at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 8:00 am
Categories: Agnisys, EDA, Events

DAC 2024 Banner

Agnisys Inc. a leader in design and verification automation for hardware development, is gearing up for an impactful presence at DAC 2024. This year’s participation will be marked by various activities designed to engage and inspire the electronic design automation (EDA) community. Attendees can look forward to our Exhibitor Forum presentation, an exciting design contest featuring our IDS-NG tool, and our sponsorship of the ‘I LOVE DAC‘. Join us for live demonstrations, interactive sessions, and hands-on experiences that underscore our commitment to innovation in design automation.

I LOVE DAC PROMOTION
We are proud to sponsor ‘I LOVE DAC‘ at this year’s DAC event. As part of our sponsorship, we are thrilled to offer 44 promo codes for access to premium Engineering Tracks at the conference. This exclusive access includes Keynotes, SKYTalks & TechTalks, Engineering Track Presentations, Engineering Track Posters, the DAC Pavilion and Exhibitor Forum, Exhibits, Tuesday Career Development Day, Hands-On Training, and DAC Networking Events. This is a limited-time offer, so take advantage of this opportunity to be at the forefront of engineering innovation. To secure one of these promo codes, then fill out the form on the Agnisys website, these codes are available on a first-come, first-served basis. Register Today!

AGNISYS DESIGN CONTEST
One of the highlights at the Agnisys booth this year is the Agnisys Design Contest, showcasing our powerful IDS-NG tool. IDS-NG is renowned for its ability to streamline digital design, eliminating the need for manual verification, validation, and integration. Participants will have the opportunity to attend a short demo of IDS-NG, demonstrating its capabilities in creating digital designs rapidly and efficiently. Following the demo, participants can test their skills by using IDS-NG to create their digital designs in a fun and competitive environment.

Participants will see how IDS-NG accelerates the design process, allowing them to create functional designs without the traditional hurdles of verification, validation, and debugging. Every participant will receive a gift, and the day will culminate in a raffle draw at 5:00 PM, offering further chances to win attractive prizes.

EXHIBITOR FORUM
At the exhibitor forum we’ll be presenting on the topic of “Object-Oriented Embedded Hardware for Operational Excellence”, Object-oriented software has made its mark in the industry. It has helped create large software systems. Coming from the Software industry it has been adopted by hardware verification in the form of languages like SystemVerilog and SystemC and methodologies like UVM. But what about embedded hardware?

This presentation will discuss how embedded hardware can be presented in an object-oriented way to firmware and lower levels of system software. We will review the industry standards and non-standard formats that are currently prevalent in this space.

Date: Wednesday 26, 2024
Time: 11:15AM – 11:45AM PDT
Location: Exhibitor Forum, Level 1 Exhibit Hall
Duration: 30 mins

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Weebit Nano at the 2024 Design Automation Conference

Weebit Nano at the 2024 Design Automation Conference
by Daniel Nenni on 06-19-2024 at 6:00 am
Categories: Events, IP, Weebit Nano

DAC 2024 Banner

Innovative Memory Architectures for AI – Don’t Miss this DAC Session!

We all know that the proliferation of AI applications is happening at an unprecedented rate while at the same time, memories aren’t scaling along with logic. This is one of many reasons that the industry is exploring new memory technologies and architectures.

When it comes to embedded non-volatile memory (NVM), the incumbent technology, flash, has reached its limits in terms of power consumption, speed, endurance and cost. It is also not scalable below 28nm, so it’s not possible to integrate flash and an AI inference engine together in a single SoC at 28nm and below for edge AI applications.

Embedded ReRAM is the logical alternative. Embedding ReRAM into an AI SoC would replace off-chip flash devices, and it can also be used to replace the large on-chip SRAM to store the AI weights and CPU firmware. Because the technology is non-volatile, there is no need to wait at boot time to load the AI model from external NVM.

ReRAM is also much denser than SRAM which makes it less expensive than SRAM per bit, so more memory can be integrated on-chip to support larger neural networks for the same die size and cost. While on-chip SRAM will still be needed for data storage, the array will be smaller and the total solution more cost-effective. With ReRAM, designers can have a single chip implementation of advanced AI in a single IC while saving die size and cost.

ReRAM will also be a building block for the future of edge AI: neuromorphic computing. In this paradigm, also called in-memory analog processing, compute resources and memory reside in the same location, so there is no need to ever move the weights. The neural network matrices become arrays of ReRAM cells, and the synaptic weights become the conductance of the NVM cells that drive the multiply operations.

Because ReRAM cells have physical and functional similarities to the synapses in the human brain, it will be possible to emulate the behavior of the human brain with ReRAM for fast real-time processing on massive amounts of data. Such a solution will be orders of magnitude more power-efficient than today’s neural network simulations on traditional processors.

At the Design Automation Conference (DAC) 2024, Gideon Intrater from Weebit Nano will go in depth on this topic during his presentation, ‘ReRAM: Enabling New Low-power AI Architectures in Advanced Nodes.’

Gideon’s presentation will be part of the session, ‘Cherished Memories: Exploring the Power of Innovative Memory Architectures for AI Applications,’ which will explore cutting-edge technologies transforming the landscape of memory design. Organized by Moshe Zalcberg of Veriest Solutions and moderated by Raul Camposano of Silicon Catalyst, other presenters include experts from RAAM Technologies and Veevx Inc.

Don’t miss this DAC session!

  • Cherished Memories: Exploring the Power of Innovative Memory Architectures for AI Applications
  • Time: 10:30 AM – 12:00 PM
  • Location: IP Room: 2012, 2nd Floor
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OPENEDGES Technology at the 2024 Design Automation Conference

OPENEDGES Technology at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 8:00 pm
Categories: Events, IP

DAC 2024 Banner

A leading memory subsystem IP provider, OPENEDGES Technology  (OPENEDGES) is set to unveil the 2.0 release of PHY Vision at the Design Automation Conference (DAC) 2024. The event will take place at the Moscone Center West, San Francisco, from June 24th to 26th, where attendees can experience firsthand the enhanced capabilities of this advanced LPDDR PHY visualization and exploration software.

PHY Vision 2.0 is a Graphical User Interface (GUI) software that allows users to configure, control, and visualize the behavior of OPENEDGES’ LPDDR PHY IPs in different operating conditions and applying analog tuning settings. Since its initial debut at last year’s DAC, PHY Vision has been upgraded with improvements in architecture, performance, and portability. The live demonstration will feature OPENEDGES’ 7nm LPDDR5X combo PHY IP and test platform, operating at a data rate of 8533 Mbps.

At OPENEDGES’ booth 2432, visitors can view a live demo of PHY Vision 2.0 and explore the many features and benefits of OPENEDGES’ LPDDR PHY IP, which include:

  • Advanced protocol availability for mature technology nodes
  • Cross-verification with OPENEDGES’ ORBIT Memory Controller (OMC)
  • Reduced silicon footprint and area requirements
  • Accelerated training time with support for firmware customization
  • Fast frequency set point (FSP) switching
  • Optimized low power states
  • Simplified integration of HARD and SOFT IP and more.

Visitors to the Moscone Center West can also learn more about OPENEDGES’ most recent PHY achievement, the successful silicon bring-up of its LPDDR5X PHY IP on 5nm process technology.

OPENEDGES’ wholly owned subsidiary, The Six Semiconductor (TSS), which specializes in developing high-speed DDR PHY IP, will also be present at the booth. TSS engineers will engage with visitors to share their insights and expertise in memory sub-system planning and implementation for low-power systems.

OPENEDGES is a total memory subsystem IP provider offering DDR memory controller, DDR PHY, On-chip Interconnect, and NPU IPs, compatible with the latest DDR technology trends. Contact OPENEDGES here to schedule a meeting at booth #2432.

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