Circuit Simulation update from Cadence at DAC

Intro
In the bloggers suite I met with John Pierce of Cadence last Wednesday to get an update on what’s new with circuit simulation at DAC this year.

Notes

News – market is growing, RF CMOS simulation is growing
– Show on RF (MTT – Microwave Technology ) this week, sharing a booth with AWR this week
– Recent news with Lorenz (EM tool to create inductors), they’re part of Connections program
– APS RF released on year ago (Parallel in the new engine)
– RF usability improved, able to do s-parameter analysis

Virtuoso APS – continued to improve, up to 16 cores
– December 2010 now you can go distributed, across machines
– No special setup required
– Uses more tokens
– Super Threading: multi-core plus distributed processing (multi-core per box)
– Typical usage: Two machines, 4 cores per machine

UltraSim – looking at next generation technologies
– Usability and speed improvements done and planned
– New developers added
– Did a new RF model

Modeling – how to model FInFET (Tri-gate)?
– Compact Modeling group involvement

Altos – acquired library characterization company
– Integrated with them last year, especially memory characterization
– Works with either Spectre or UltraSim or internal simulator

Growth – Altos had 11 out of 20 top semi companies for library characterization
– Good collaboration over past 12 months too (Jim Mccanney)

Spectre – New in last year is APS and distributed
– Shares models with UltraSim

AMS Designer – transistor simulation plus HDL
– Real number modeling (standard part of SystemVerilog) lets you model analog effects in a logic verification environment
– Did a paper at the ARM conference last year, DVCON this year (assertions plus real number modeling)
o Help ADC test bench verification
– Adoption of real number modeling is driven by the design style more than the technology
– Work with designersguide.com on training the next generation of AMS designers, classes tailored to the client and offer consulting services
– Knowlent went out of business as Analog Verification IP (too limited of an approach, not portable)
– How to influence the next generation, Universities

Parasitic Aware Design – simulation with real parasitic, as early as possible in the flow
– Quickly go from schematic to layout to extracted parasitic, better simulation results
– Virtuoso can help manage the whole parasitic flow

IMS Chips (Germany) – Used Custom Designer, then went back to Virtuoso (Feb 2011)

Wolfson (UK) – Uses SNPS digital tools, and internal analog tools. They evaluated Custom Designer but choose Virtuoso plus digital flows.

Summary
Cadence has plenty of competitors in the circuit simulation space so they continue to update and innovate their tools to stay current. Only three vendors offer an integrated co-simulation between SPICE and a widely-adopted HDL simulator (Cadence, Mentor, Synopsys).