Accelerating Connectivity with the Versal Adaptive SOC Network on Chip Workshop

Accelerating Connectivity with the Versal Adaptive SOC Network on Chip Workshop
by Admin on 06-12-2025 at 1:31 pm

Accelerating Connectivity with the Versal Adaptive SOC Network on Chip Workshop

This workshop introduces the AMD Versal network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move

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Webinar: Maximizing RFSoC Potential with Functionality and Configurability

Webinar: Maximizing RFSoC Potential with Functionality and Configurability
by Admin on 06-12-2025 at 1:28 pm

Description

BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.

Join us to explore the functionality and configurability of the AMD Zynq UltraScale+ RFSoC. With the RFSoC, configuring data converters is crucial for advanced system development, but the complexity often overwhelms… Read More


Designing DSP Applications with Versal AI Engines Workshop

Designing DSP Applications with Versal AI Engines Workshop
by Admin on 06-12-2025 at 1:17 pm

Designing DSP Applications with Versal AI Engines Workshop

This workshop covers the AMD Versal AI Engine architecture and using the AI Engine DSP Library, system partitioning, rapid prototyping, and custom coding of AI Engine kernels. Developing AI Engine DSP designs using AMD Vitis Model Composer is also demonstrated.

The

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Webinar: Basic Booting for AMD Zynq and Versal Devices with Practical Tips and Techniques

Webinar: Basic Booting for AMD Zynq and Versal Devices with Practical Tips and Techniques
by Admin on 06-12-2025 at 1:15 pm

Description

BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.

Are FPGA booting challenges causing frustrating delays and leaving you uncertain about project timelines? Have you spent countless hours wrestling with boot image creation, only to encounter hardware dependencies… Read More


Vivado Quick Start with Versal Devices Workshop

Vivado Quick Start with Versal Devices Workshop
by Admin on 06-12-2025 at 1:11 pm

This online workshop introduces key concepts, tools, and techniques required for design and development using the AMD Vivado™ Design Suite for FPGAs, SoCs, and adaptive SoCs.

The emphasis of this course is on:

  • Introduction to designing FPGAs with the Vivado Design Suite
  • Creating a Vivado project with source files
  • Introduction
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Upcoming Webinar: Accelerating Semiconductor Design with Generative AI and High-Level Abstraction

Upcoming Webinar: Accelerating Semiconductor Design with Generative AI and High-Level Abstraction
by Daniel Nenni on 03-27-2025 at 10:00 am

RDA SemiWikiblog graphic

We have been hearing so much lately about the power of AI and the potential of technologies like agentic AI to address the productivity gap and complexities of semiconductor designs of today and tomorrow.  Currently, however, the semiconductor industry has been slow to adopt generative and agentic AI for RTL design code.   There… Read More


WEBINAR: Silicon Area Matters!

WEBINAR: Silicon Area Matters!
by Daniel Nenni on 08-14-2024 at 8:00 am

SemiWiki Flex Logix Webinar

When designing IP for system-on-chip (SoC) and application-specific integrated circuit (ASIC) implementations, IP designers strive for perfection. Optimal engineering often yields the smallest die area, thereby reducing both cost and power consumption while maximizing performance.

Similarly, when incorporating embedded… Read More


LIVE WEBINAR Maximizing SoC Energy Efficiency: The Role of Realistic Workloads and Massively Parallel Power Analysis

LIVE WEBINAR Maximizing SoC Energy Efficiency: The Role of Realistic Workloads and Massively Parallel Power Analysis
by Daniel Nenni on 07-03-2024 at 2:00 pm

The Role of Realistic Workloads and Massively Parallel Power Analysis

As the complexity of modern System-on-Chip (SoC) designs continues to rise, achieving energy efficiency measured as performance per watt has become a crucial design goal. With the increasing demand for powerful, multifunctional chips, balancing performance with power consumption has become essential. Realistic workloads… Read More


Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points

Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points
by Daniel Payne on 11-02-2023 at 10:00 am

Worst case point min

IC designers are tasked with meeting specifications like robustness in SRAM bit cells where the probability of a violation are lower than 1 part-per-billion (1 ppb). Another example of robustness is a Flip-Flop register that must have a probability of specification violation lower than 1 part-per-million (1 ppm). Using Monte… Read More


WEBINAR: An Ideal Neural Processing Engine for Always-sensing Deployments

WEBINAR: An Ideal Neural Processing Engine for Always-sensing Deployments
by Daniel Nenni on 05-29-2023 at 10:00 am

Option 1

Always-sensing cameras are a relatively new method for users to interact with their smartphones, home appliances, and other consumer devices. Like always-listening audio-based Siri and Alexa, always-sensing cameras enable a seamless, more natural user experience. However, always-sensing camera subsystems require specialized… Read More