This webinar shows how engineers can use a unified EOE simulation workflow in Keysight Advanced Design System (ADS) to co-design and validate high-speed Ethernet systems across both electronic and photonic domains for faster, more accurate development.
Signal integrity engineers
This webinar showcases how the Keysight Technologies SOS extension integrates design data management directly into Visual Studio Code, helping digital design and verification teams streamline RTL and HDL workflows without leaving their coding environment.
Digital design engineers
The Inference Stack Can Talk. Learn How to Listen.
AI has entered the inference era.
For years the industry focused on training models. But today the real challenge is running AI workloads in production at scale.
In this webinar, you’ll have the opportunity to learn how to decode the signals from your inference
Step into the future of semiconductor design management with IPLM: Future Forward, a product-led webinar showcasing the latest developments in Perforce IPLM. This focused session is designed to show how modern teams can tackle growing design complexity while still accelerating innovation.
Hosted by IPLM… Read More
**Work Email Required for Registration**
Embedded systems programs rarely fail because any one team lacks capability. They fail because critical engineering artifacts drift out of alignment over time and distance.
This includes requirements, architecture, implementation, verification, hardware bring-up, firmware,… Read More
The upcoming webinar “Intelligent Networks: Power, Reliability, and Maintenance in Telecom” will focus on how telecommunications networks are adapting to growing demands for efficiency, resilience, and scalability. As telecom operators expand 5G deployments, integrate cloud-native architectures, and prepare for AI-driven… Read More
The explosive growth of AI and accelerated computing is placing unprecedented demands on system-on-chip (SoC) design. Modern AI workloads require extremely high bandwidth, ultra-low latency, and energy-efficient data movement across increasingly heterogeneous architectures. As SoCs scale to incorporate clusters of… Read More
An engineering change order, or ECO in the context of ASIC design is a way to modify or patch a design after layout without needing to re-implement the design from its starting point. There are many reasons to use an ECO strategy. Some examples include correcting errors that are found in post-synthesis verification, optimizing … Read More
This webinar, in partnership with Easy-Logic Technology, is to address the complexities and challenges associated with functional ECO (Engineering Change Order) in ASIC design, with a particular focus on mixed-signal designs.
The webinar begins by highlighting the critical role of mixed-signal chips in modern applications,… Read More
Edge AI is rapidly transforming how intelligent solutions are designed, from smart home devices to autonomous vehicles, healthcare gadgets, and industrial IoT. Yet, architects, chip designers, and product managers frequently grapple with a common and daunting challenge: creating efficient, high-performance AI solutions… Read More
