Tag: webinar

Webinar: 448G PAM4: The Future of 3.2T Data Centers

Webinar: 448G PAM4: The Future of 3.2T Data Centers
by Admin on 08-27-2025 at 8:13 pm

About this event

Join industry experts from NTT Innovative Devices, Lumentum, and Keysight to discuss their historic demonstration of 448g / lane signaling over PAM4 — a cross-continental collaboration that’s laying the foundation for the next generation of AI data centers and high-speed Ethernet.

Who should attend this event?

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Webinar: Optimizing antenna performance with Infineon’s antenna tuners and cross switch solutions

Webinar: Optimizing antenna performance with Infineon’s antenna tuners and cross switch solutions
by Admin on 08-27-2025 at 8:10 pm

About the webinar:

With the growing demand for devices operating across multiple frequency bands, optimizing antenna radiation efficiency is essential for delivering reliable, high-performance connectivity.

Join our webinar to discover how Infineon’s antenna tuning switches can help you overcome antenna design

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WEBINAR: Edge AI Optimization: How to Design Future-Proof Architectures for Next-Gen Intelligent Devices

WEBINAR: Edge AI Optimization: How to Design Future-Proof Architectures for Next-Gen Intelligent Devices
by Daniel Nenni on 07-03-2025 at 10:00 am
Categories: Ceva, Events, IP

Ceva webinar AI Arch SEMI 400X400 250625

Edge AI is rapidly transforming how intelligent solutions are designed, from smart home devices to autonomous vehicles, healthcare gadgets, and industrial IoT. Yet, architects, chip designers, and product managers frequently grapple with a common and daunting challenge: creating efficient, high-performance AI solutions… Read More

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WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs

WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs
by Daniel Nenni on 07-03-2025 at 6:00 am
Categories: CAST, Events, IP

CAST Compression IP Webinar 400x400

In today’s data-driven systems—from cloud storage and AI accelerators to automotive logging and edge computing—every byte counts. The exponential growth in data volumes, real-time processing demands, and constrained bandwidth has made efficient, lossless data compression a mission-critical requirement. Software-based… Read More

Essential Debugging Techniques Workshop

Essential Debugging Techniques Workshop
by Admin on 06-12-2025 at 1:48 pm

Essential Debugging Techniques Workshop

This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado

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Webinar: Mastering Clock Domain Crossings (CDC) and Synchronization Techniques

Webinar: Mastering Clock Domain Crossings (CDC) and Synchronization Techniques
by Admin on 06-12-2025 at 1:45 pm

Description

Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break down CDC fundamentals, explore best practices for managing single-bit and bus CDCs, and demonstrate how to leverage Xilinx… Read More

From Theory to Practice: Applying Timing Constraints Workshop

From Theory to Practice: Applying Timing Constraints Workshop
by Admin on 06-12-2025 at 1:42 pm

From Theory to Practice: Applying Timing Constraints Workshop

Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover how to use features in Vivado, clock domain crossing strategies, and how to get the most out of static timing analysis for Versal devices.

This… Read More

Webinar: Exploring AMD Kria SOM for ROS 2 Multi-Node Communications with TSN Acceleration

Webinar: Exploring AMD Kria SOM for ROS 2 Multi-Node Communications with TSN Acceleration
by Admin on 06-12-2025 at 1:40 pm

Description

BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.

Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for your applications. In this session, you’ll explore the TSN-ROS application and its role in enhancing communications… Read More

Achieving Timing Closure in FPGA Designs Workshop

Achieving Timing Closure in FPGA Designs Workshop
by Admin on 06-12-2025 at 1:37 pm

Achieving Timing Closure in FPGA Designs Workshop

Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achieve reliable timing closure.

Gain hands-on experience … Read More