Webinar: From Power Integrity Signoff to Design Optimization: The Growing Role of Sigma Technologies

Webinar: From Power Integrity Signoff to Design Optimization: The Growing Role of Sigma Technologies
by Admin on 07-20-2026 at 4:27 pm

Featured Speakers:

  • Jerome Toublanc, Product Management, Principal, Synopsys

As advanced-node and multi-die designs push power delivery networks to their limits, accurately understanding voltage behavior has become essential for both signoff confidence and design optimization. Traditional approaches often struggle… Read More


Webinar: Compensating for PCB laminate anisotropy in SI calculations

Webinar: Compensating for PCB laminate anisotropy in SI calculations
by Admin on 07-16-2026 at 6:19 pm

Why Your Impedance Models May Be Less Accurate Than You Think

For many years, the PCB industry has accepted dielectric values without fully understanding how they were measured—or whether they’re the right values for impedance modeling. This webinar explores what that means for today’s high-speed designs.

As … Read More


Webinar: Enabling Agile CI/CD in Chip Design: Running Synopsys EDA Flows from GitHub

Webinar: Enabling Agile CI/CD in Chip Design: Running Synopsys EDA Flows from GitHub
by Admin on 07-13-2026 at 6:22 pm

Featured Speakers:

  • Achim Nohl, Distinguished Architect, Synopsys
  • Varun Shah, Product Management Director, Synopsys

Hardware teams are moving to GitHub, CI/CD, and Pull Request-driven workflows, but EDA tools often sit outside that loop – breaking collaboration and slowing agentic automation.

This Synopsys webinar

… Read More

How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too Late

How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too Late
by Mike Gianfagna on 06-25-2026 at 10:00 am

How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too Late

Embedded systems programs often fail because critical engineering documentation drifts out of alignment over time and distance. This results in a team that is correctly following the wrong instructions. All forms of engineering documentation suffer from this problem, and it really is the silent killer of many programs.

llmda.ai… Read More


IPLM: Future Forward Webinar May 19th

IPLM: Future Forward Webinar May 19th
by Daniel Nenni on 05-12-2026 at 6:00 am

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Step into the future of semiconductor design management with IPLM: Future Forward, a product-led webinar showcasing the latest developments in Perforce IPLM. This focused session is designed to show how modern teams can tackle growing design complexity while still accelerating innovation.

Hosted by IPLM… Read More


Intelligent Networks: Power, Reliability, and Maintenance in Telecom — Webinar Preview

Intelligent Networks: Power, Reliability, and Maintenance in Telecom — Webinar Preview
by Daniel Nenni on 02-19-2026 at 2:00 pm

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The upcoming webinar “Intelligent Networks: Power, Reliability, and Maintenance in Telecom” will focus on how telecommunications networks are adapting to growing demands for efficiency, resilience, and scalability. As telecom operators expand 5G deployments, integrate cloud-native architectures, and prepare for AI-driven… Read More


Live Webinar: Considerations When Architecting Your Next SoC: NoC with Arteris and Aion Silicon

Live Webinar: Considerations When Architecting Your Next SoC: NoC with Arteris and Aion Silicon
by Daniel Nenni on 11-27-2025 at 8:00 am

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The explosive growth of AI and accelerated computing is placing unprecedented demands on system-on-chip (SoC) design. Modern AI workloads require extremely high bandwidth, ultra-low latency, and energy-efficient data movement across increasingly heterogeneous architectures. As SoCs scale to incorporate clusters of… Read More


Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICs

Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICs
by Mike Gianfagna on 09-11-2025 at 10:00 am

Webinar Preview – Addressing Functional ECOs for Mixed Signal ASICs

An engineering change order, or ECO in the context of ASIC design is a way to modify or patch a design after layout without needing to re-implement the design from its starting point. There are many reasons to use an ECO strategy. Some examples include correcting errors that are found in post-synthesis verification, optimizing … Read More