Analyzing All of those IC Parasitic Extraction Results

Analyzing All of those IC Parasitic Extraction Results
by Daniel Payne on 03-30-2017 at 12:00 pm

Back at DAC in 2011 I first started to hear about this EDA company named edXact that specialized in reducing and analyzing IC parasitic extraction results. So Silvaco acquired edXact and I wanted to get an update on what is new with their EDA tools that help help you to analyze and manage the massive amount of extracted RLC and even K … Read More


Seven Reasons to Use FPGA Prototyping for ASIC Designs

Seven Reasons to Use FPGA Prototyping for ASIC Designs
by Daniel Payne on 03-28-2017 at 12:00 pm

Using an FPGA to prototype your next hardware design is a familiar concept, extending all the way back to the time that the first FPGAs were being produced by Xilinx and Altera. There are multiple competitors in the marketplace for FPGA prototyping, so I wanted to discern more about what the German-based company PRO DESIGN had to … Read More


How to Design a Custom SoC with Analog, webinar from ARM and Tanner EDA

How to Design a Custom SoC with Analog, webinar from ARM and Tanner EDA
by Daniel Payne on 03-23-2017 at 12:00 pm

Leading edge SoC designs can contain billions of transistors, cost over $10M to design, and take over 18 months to deliver, but not all SoCs require that much complexity, cost and time. In fact, there is a growing class of SoC designs that integrate the popular ARM Cortex-M0 processor along with analog blocks that work with sensors… Read More


Six Reasons to Consider Using FPGA Prototyping for ASIC Designs

Six Reasons to Consider Using FPGA Prototyping for ASIC Designs
by Daniel Payne on 03-15-2017 at 12:00 pm

There’s no doubt that programmable logic in FPGAs have transformed our electronics industry for the better. If you do ASIC designs then there’s always the pressure of getting first silicon correct, with no functional or timing bugs, because bugs will cause expensive re-spins and delay time to market. ASIC designers… Read More


Webinar: CEVA on basestation design for 5G NR

Webinar: CEVA on basestation design for 5G NR
by Bernard Murphy on 03-15-2017 at 7:00 am

Conventional wisdom is that 5G is still somewhere on the hype curve – expected to arrive someday but still not a near-term technology. As is often the case, conventional wisdom seems to be wrong. Coming out of this year’s Mobile World Congress in Barcelona, semiconductor and carrier heavyweights have committed to accelerate deploymentRead More


Securing Your IoT System using ARM

Securing Your IoT System using ARM
by Daniel Payne on 03-14-2017 at 12:00 pm

I’ll never forget reading about and experiencing the October 21, 2016 Distributed Denial of Service (DDoS) attacks which slowed and shut down a lot of the Internet. On that particular attack the target was to shut down the Domain Name System (DNS). Traffic for this massive DDoS attack came from IoT devices which were unsecured… Read More


What You Don’t Know about Parasitic Extraction for IC Design

What You Don’t Know about Parasitic Extraction for IC Design
by Daniel Payne on 02-23-2017 at 7:00 am

Out of college my first job was doing circuit design at the transistor-level with Intel, and to get accurate SPICE netlists for simulation we had to manually count the squares of parasitic interconnect for diffusion, poly-silicon and metal layers. Talk about a burden and chance for mistakes, I’m so thankful that EDA companies… Read More


TCAD Simulation of Organic Optoelectronic Devices

TCAD Simulation of Organic Optoelectronic Devices
by Daniel Payne on 01-20-2017 at 4:00 pm

In my office there are plenty of LED displays for me to look at throughout the day: three 24″ displays from Viewsonic, a 15″ display from Apple, an iPad, a Samsung Galaxy Note 4, a Nexus tablet, a Garmin 520 bike computer, and a temperature display. LED and OLED displays are ubiquitous in all sorts of consumer electronics,… Read More


Real Time Virtualization, How Hard Can it Be?

Real Time Virtualization, How Hard Can it Be?
by Daniel Payne on 12-26-2016 at 12:00 pm

My first exposure to running something virtual on a computer was when I decided to run the Windows OS on my MacBook Pro using software provided by Parallels. With that virtualization I was able to run the Quicken app under Windows on my MacBook Pro, along with the popular Internet Explorer web browser. The app performance on virtualized… Read More


ARM and Mentor talk about Real Time Virtualization, Webinar

ARM and Mentor talk about Real Time Virtualization, Webinar
by Daniel Payne on 12-08-2016 at 12:00 pm

Processor cores come in a wide variety of speeds, performance and capabilities, so it may take you some time to find the proper processor for your system. Let’s say that you are designing a product for the industrial, automotive, military or medical markets that has an inherent requirement for safety, security and reliability… Read More