Cadence® Janus™ Network-on-Chip (NoC)

Cadence® Janus™ Network-on-Chip (NoC)
by Kalar Rajendiran on 07-23-2024 at 10:00 am

Design Flow when using Janus NoC

A Network-on-Chip (NoC) IP addresses the challenges of interconnect complexity in SoCs by significantly reducing wiring congestion and providing a scalable architecture. It allows for efficient communication among numerous initiators and targets with minimal latency and high speed. A NoC facilitates design changes, enabling… Read More