AI can compress the path to tape-out. The next challenge is compressing physical realization.
Something important is beginning to happen in semiconductor development: the design cycle itself is becoming compressible.
AI-assisted engineering can accelerate architecture exploration, RTL development, verification, physical… Read More
So… , we’re 4 months before tapeout. You were assigned to close place & route on three complex key blocks. You have 15 machines for the job, 5 per block.
You send your first batch, 5 runs per block. You’re not very surprised that your first batch fails. You modify the scripts, and run another batch. And… (Surprise… Read More
As semiconductor designs for many popular products move into smaller process nodes, the need for effective and rapid design closure is increasing. The SOCs used for many consumer and industrial applications are moving to FinFET nodes from 16 to 7nm and with that comes greater challenges in obtaining design closure. einfochips,… Read More
