Synopsys Executive Forum: Driving Silicon and Systems Engineering Innovation

Synopsys Executive Forum: Driving Silicon and Systems Engineering Innovation
by Kalar Rajendiran on 04-09-2025 at 10:00 am

Sassine Keynote (with Satya)

The annual SNUG (Synopsys Users Group) conference, now in its 35th year, once again brought together key stakeholders to showcase accomplishments, discuss challenges, and explore opportunities within the semiconductor and electronics industry. With approximately 2,500 attendees, SNUG 2025 served as a dynamic hub for collaboration… Read More


Webinar: PCIe 7.0? Understanding Why Now is the Time to Transition

Webinar: PCIe 7.0? Understanding Why Now is the Time to Transition
by Admin on 04-07-2025 at 3:16 am

Join us for an Q&A technical session with Madhumita Sanyal, technical product director of HPC IP, and Richard Solomon, principal product manager and vice-president of PCI-SIG, discussing the pivotal role of PCIe 7.0 in enabling high-performance computing, AI clusters, and next-gen chip designs. This session will explore

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Podcast EP281: A Master Class in the Evolving Ethernet Standard with Jon Ames of Synopsys

Podcast EP281: A Master Class in the Evolving Ethernet Standard with Jon Ames of Synopsys
by Daniel Nenni on 04-04-2025 at 10:00 am

Dan is joined by Jon Ames, principal product manager for the Synopsys Ethernet IP portfolio. Jon has been working in the communications industry since 1988 and has led engineering and marketing activities from the early days of switched Ethernet to the latest data center and high-performance computing Ethernet technologies.… Read More


Evolution of Memory Test and Repair: From Silicon Design to AI-Driven Architectures

Evolution of Memory Test and Repair: From Silicon Design to AI-Driven Architectures
by Kalar Rajendiran on 04-01-2025 at 6:00 am

STAR Memory System (SMS) Solution

Memory testing in the early days of computing was a relatively straightforward process. Designers relied on simple, deterministic approaches to verify the functionality of memory modules. However, as memory density increased and systems became more complex, the likelihood of faults also rose. With advancements in memory… Read More


Webinar: Verifying AI Designs – Solving the Challenge of Quadrillions of Verification Cycles

Webinar: Verifying AI Designs – Solving the Challenge of Quadrillions of Verification Cycles
by Admin on 03-28-2025 at 12:31 pm

Today’s AI designs stress verification teams to an unprecedented extent. The compound complexity from software, hardware, interfaces, and architecture options leads to the challenge of running quadrillions of verification cycles across IP, sub-systems, SoCs, and Multi-die designs. Learn how leaders from AMD, Arm, Nvidia,

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Synopsys Expands Hardware-Assisted Verification Portfolio to Address Growing Chip Complexity

Synopsys Expands Hardware-Assisted Verification Portfolio to Address Growing Chip Complexity
by Kalar Rajendiran on 02-25-2025 at 6:00 am

Synopsys HAV Product Family

Last week, Synopsys announced an expansion of their Hardware-Assisted Verification (HAV) portfolio to accelerate semiconductor design innovations. These advancements are designed to meet the increasing demands of semiconductor complexity, enabling faster and more efficient verification across software and hardware… Read More


Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?

Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?
by Kalar Rajendiran on 01-28-2025 at 6:00 am

Synopsys Predictions for Multi Die Designs in 2025

Predictions in technology adoption often hinge on a delicate balance between technical feasibility and market dynamics. While business considerations play a pivotal role, the technical category reasons for the success or failure of a prediction are more tangible and often easier to identify—if scrutinized with care. However,… Read More


A Deep Dive into SoC Performance Analysis: Optimizing SoC Design Performance Via Hardware-Assisted Verification Platforms

A Deep Dive into SoC Performance Analysis: Optimizing SoC Design Performance Via Hardware-Assisted Verification Platforms
by Lauro Rizzatti on 01-22-2025 at 10:00 am

A Deep Dive into SoC Performance Analysis Part 2 Figure 1

Part 2 of 2 – Performance Validation Across Hardware Blocks and Firmware in SoC Designs

Part 2 explores the performance validation process across hardware blocks and firmware in System-on-Chip (SoC) designs, emphasizing the critical role of Hardware-Assisted Verification (HAV) platforms. It outlines the validation workflowRead More