Synopsys and AMD were recently selected by the World Economic Forum for inclusion in the WEF’s MINDS (Meaningful, Intelligent, Novel, Deployable Solutions) AI program, recognizing their leadership and real-world impact in applying generative and agentic AI to semiconductor design and engineering. This distinction places… Read More
For decades, One-Time Programmable (OTP) memory has been viewed as a foundational element of hardware security. Because OTP can be written only once and cannot be modified afterward, it has traditionally been trusted to store cryptographic keys, secure boot code, device identity, and configuration data. Permanence was often… Read More
Date: Feb 04, 2026 | 9:00 AM PST
Featured Speakers:
Our upcoming Synopsys webinar features an exciting real-world case study showcasing Synopsys IP and EDA tools with UCIe-based chiplets on advanced
Date: Feb 05, 2026 | 9:00 AM PST
Featured Speakers:
Discover how UALink enables open, scalable, secure interconnects for AI workloads—and how Synopsys IP and VIP accelerate adoption.
Why You Should Attend:
For more than three decades, SNUG Silicon Valley has connected engineers, designers, and thought leaders with technical experts to network and share best practices for tackling design and verification challenges using Synopsys technologies. The Call for Content invites you to showcase how you are developing tomorrow’s products… Read More
The rapid evolution of RISC-V processors has introduced unprecedented verification challenges. Modern high-end RISC-V cores now incorporate complex features such as vector and hypervisor extensions, virtual memory systems, multi-level caches, advanced interrupt architectures, and multi-hart out-of-order execution.… Read More
Cisco’s relentless push toward higher-performance networking silicon has placed extraordinary demands on its ASIC design methodology. As transistor densities continue to rise across advanced SoCs, traditional design-time guardbands are no longer sufficient to ensure long-term reliability, consistent performance,
We are pleased to offer two webinar sessions for your convenience. Please choose the time that best fits your schedule:
10:00AM – 12:00PM CET (session #1 for EMEA/APAC)
10:00AM – 12:00PM PST (session #2 for NA)
Featured Speakers:
Date: Jan 14, 2026 | 10:00 AM PST
Featured Speakers:
As System-on-Chip (SoC) designs become increasingly complex, meeting test quality
As AI and HPC systems scale to thousands of CPUs, GPUs, and accelerators, interconnect performance increasingly determines end-to-end efficiency. Training and inference pipelines rely on low-latency coordination, high-bandwidth memory transfers, and rapid communication across heterogeneous devices. With model sizes… Read More
