Hot on the heels of DVConUS 2025, the 35th annual Synopsys User Group (SNUG) Conference made its mark as a defining moment in the evolution of Synopsys—and the broader electronic design automation (EDA) industry. This year’s milestone event not only underscored Synopsys’ continued innovation but also affirmed the vision… Read More
Tag: synopsys
Design IP Market Increased by All-time-high: 20% in 2024!
Design IP revenues achieved $8.5B in 2024 and this is an all-time-high growth of 20%. Wired Interface is still driving Design IP growth with 23.5% but we see the Processor category also growing by 22.4% in 2024. This is consistent with the Top 4 IP companies made of ARM (mostly focused on processor) and a team leading wired interface… Read More
Synopsys Executive Forum: Driving Silicon and Systems Engineering Innovation
The annual SNUG (Synopsys Users Group) conference, now in its 35th year, once again brought together key stakeholders to showcase accomplishments, discuss challenges, and explore opportunities within the semiconductor and electronics industry. With approximately 2,500 attendees, SNUG 2025 served as a dynamic hub for collaboration… Read More
Webinar: PCIe 7.0? Understanding Why Now is the Time to Transition
Join us for an Q&A technical session with Madhumita Sanyal, technical product director of HPC IP, and Richard Solomon, principal product manager and vice-president of PCI-SIG, discussing the pivotal role of PCIe 7.0 in enabling high-performance computing, AI clusters, and next-gen chip designs. This session will explore
Podcast EP281: A Master Class in the Evolving Ethernet Standard with Jon Ames of Synopsys
Dan is joined by Jon Ames, principal product manager for the Synopsys Ethernet IP portfolio. Jon has been working in the communications industry since 1988 and has led engineering and marketing activities from the early days of switched Ethernet to the latest data center and high-performance computing Ethernet technologies.… Read More
Evolution of Memory Test and Repair: From Silicon Design to AI-Driven Architectures
Memory testing in the early days of computing was a relatively straightforward process. Designers relied on simple, deterministic approaches to verify the functionality of memory modules. However, as memory density increased and systems became more complex, the likelihood of faults also rose. With advancements in memory… Read More
Webinar: Verifying AI Designs – Solving the Challenge of Quadrillions of Verification Cycles
Today’s AI designs stress verification teams to an unprecedented extent. The compound complexity from software, hardware, interfaces, and architecture options leads to the challenge of running quadrillions of verification cycles across IP, sub-systems, SoCs, and Multi-die designs. Learn how leaders from AMD, Arm, Nvidia,
SNUG Taiwan 2025
Connecting the Synopsys User Community
Since 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Systems. Today, as the electronics industry’s largest user conference, SNUG brings together over 12,000 Synopsys tool and technology users across North America,
SNUG Europe 2025
Connecting the Synopsys User Community
Since 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Systems. Today, as the electronics industry’s largest user conference, SNUG brings together over 12,000 Synopsys tool and technology users across North America,
Synopsys Expands Hardware-Assisted Verification Portfolio to Address Growing Chip Complexity
Last week, Synopsys announced an expansion of their Hardware-Assisted Verification (HAV) portfolio to accelerate semiconductor design innovations. These advancements are designed to meet the increasing demands of semiconductor complexity, enabling faster and more efficient verification across software and hardware… Read More