Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation

Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation
by Daniel Nenni on 10-01-2025 at 10:00 am

UNDER EMBARGO 1PM PT Sept 24 Synopsys TSMC OIP 2025 (1)

In a rapidly evolving semiconductor landscape, where AI demands unprecedented computational power and efficiency, Synopsys has deepened its partnership with TSMC to pioneer advancements in AI-driven designs and multi-die systems. Announced during the TSMC OIP Ecosystem Summit last week, this collaboration leverages … Read More


AI Everywhere in the Chip Lifecycle: Synopsys at AI Infra Summit 2025

AI Everywhere in the Chip Lifecycle: Synopsys at AI Infra Summit 2025
by Kalar Rajendiran on 09-30-2025 at 10:00 am

Godwin Talk Summary AI Infra Summit 2025

At the AI Infra Summit 2025, Synopsys showed how artificial intelligence has become inseparable from the process of creating advanced silicon. The company’s message was clear: AI is an end-to-end engine that drives every phase of chip development. Three Synopsys leaders illustrated this from distinct vantage points. Godwin… Read More


Webinar: ML-Enhanced TCAD Calibration With 10x Reduction in Time to Results

Webinar: ML-Enhanced TCAD Calibration With 10x Reduction in Time to Results
by Admin on 09-30-2025 at 12:14 am

Date: Oct 15, 2025 5:00 PM PST

Featured Speakers:

  • Saurabh Suryavanshi, Product Manager, Synopsys
  • Youngkwon Cho, Senior Staff Engineer, Synopsys
  • Dipanjan Basu, Principal Engineer, Synopsys

Calibration is an essential part of enabling TCAD products usages inside Semiconductor fab. Synopsys has been leading the development

Read More

Synopsys Collaborates with TSMC to Enable Advanced 2D and 3D Design Solutions

Synopsys Collaborates with TSMC to Enable Advanced 2D and 3D Design Solutions
by Daniel Nenni on 09-29-2025 at 6:00 am

synopsys tsmc oip 2025 leading the next wave of ai and multi die innovation for tsmc advanced node designs

Synopsys has deepened its collaboration with TSMC certifying the Ansys portfolio of simulation and analysis tools for TSMC’s cutting-edge manufacturing processes including N3C, N3P, N2P, and A16. This partnership empowers chip designers to perform precise final checks on designs, targeting applications in AI acceleration,… Read More


The Impact of AI on Semiconductor Startups

The Impact of AI on Semiconductor Startups
by Kalar Rajendiran on 09-23-2025 at 6:00 am

AI Infra Summit 2025 Banner

At the AI Infra Summit 2025 was a panel conversation that captured the semiconductor industry’s anxieties and hopes. The session, titled “The Impact of AI on Semiconductor Startups,” examined how artificial intelligence is transforming not just what chips can do, but how we design them.

The backdrop is stark. Developing a leading-edge… Read More


Webinar: IP Design Considerations for Real-Time Edge AI Systems

Webinar: IP Design Considerations for Real-Time Edge AI Systems
by Admin on 09-22-2025 at 5:07 pm

*Work Email Required*

Edge AI systems increasingly require on-chip integration of large-capacity memory, compute engines, and inference-optimized accelerators—all within strict power, latency, and footprint constraints. This webinar provides a an overview of IP architecture and integration methodologies that support… Read More


Synopsys Announces Expanding AI Capabilities and EDA AI Leadership

Synopsys Announces Expanding AI Capabilities and EDA AI Leadership
by Daniel Nenni on 09-12-2025 at 6:00 am

Synopsys.ai Copilot Customer Impact

In the fast-paced semiconductor industry Synopsys has redefined EDA with its Synopsys.ai Copilot, a generative AI tool. Since its launch in November 2023, and yes I was at the launch and very skeptical, Copilot has evolved to address the industry’s growing design complexity and projected 15-30% workforce gap by 2030. Let’s… Read More


The Rise, Fall, and Rebirth of In-Circuit Emulation (Part 1 of 2)

The Rise, Fall, and Rebirth of In-Circuit Emulation (Part 1 of 2)
by Lauro Rizzatti on 09-11-2025 at 6:00 am

The Rise, Fall, and Rebirth of In Circuit Emulation Part 1 Figure 1

Introduction: The Historical Roots of Hardware-Assisted Verification

The relentless pace of semiconductor innovation continues to follow an unstoppable trend: the exponential growth of transistor density within a given silicon area. This abundance of available semiconductor fabric has fueled the creativity of design… Read More


Webinar: Why Choose PCIe 5.0 for Power, Performance, and Bandwidth at the Edge?

Webinar: Why Choose PCIe 5.0 for Power, Performance, and Bandwidth at the Edge?
by Admin on 09-05-2025 at 4:02 am

Featured Speakers:

  • Gustavo Pimentel, Principal Product Marketing Manager, Synopsys

As edge, mobile and automotive applications demand faster data processing, lower latency, and reduced power consumption, PCI Express® 5.0 has emerged as the optimal interconnect standard. Doubling the data rate of PCIe 4.0 while enabling

Read More

Webinar: Static Verification of RTL DFT Connectivity – Getting it Right the First Time!

Webinar: Static Verification of RTL DFT Connectivity – Getting it Right the First Time!
by Admin on 09-04-2025 at 1:39 am

Featured Speakers:

  • Kiran Vittal, Synopsys
  • Ayush Goyal, Synopsys

As System-on-Chip (SoC) designs become increasingly complex, ensuring reliable Design-for-Test (DFT) connectivity at the RTL stage is more important than ever. This Synopsys webinar will demonstrate how static verification techniques, powered by TestMAX™

Read More