Enhancing System Reliability with Digital Twins and Silicon Lifecycle Management (SLM)

Enhancing System Reliability with Digital Twins and Silicon Lifecycle Management (SLM)
by Kalar Rajendiran on 12-09-2024 at 6:00 am

Synopsys SLM Solution Components

As industries become more reliant on advanced technologies, the importance of ensuring the reliability and longevity of critical systems grows. Failures in components, whether in autonomous vehicles, high performance computing (HPC), healthcare devices, or industrial automation, can have far-reaching consequences.… Read More


SystemReady Certified: Ensuring Effortless Out-of-the-Box Arm Processor Deployments

SystemReady Certified: Ensuring Effortless Out-of-the-Box Arm Processor Deployments
by Lauro Rizzatti on 12-05-2024 at 10:00 am

SystemReady Certified Ensuring Out of the Box Effortless Arm Processors Deployments Figure 1

When contemplating the Lego-like hardware and software structure of a leading system-on-chip (SoC) design, a mathematically inclined mind might marvel at the tantalizing array of combinatorial possibilities among its hardware and software components. In contrast, the engineering team tasked with its validation may have… Read More


Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early Adopters

Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early Adopters
by Daniel Nenni on 11-06-2024 at 10:00 am

banner for webinar

The demand for high-performance computing (HPC), data centers, and AI-driven applications has fueled the rise of 2.5D and 3D multi-die designs, offering superior performance, power efficiency, and packaging density. However, these benefits come with myriads of challenges, such as multi-physics, which need to be addressed.… Read More


Webinar: Efficient and Robust Memory Verification in Modern SoCs Using Formal Equivalence Checker

Webinar: Efficient and Robust Memory Verification in Modern SoCs Using Formal Equivalence Checker
by Admin on 11-05-2024 at 5:51 pm

With the increasing complexity and importance of memories in modern ICs, there is a clear need for specialized tools and techniques for the design and verification of embedded memory blocks. Traditional methods like SPICE simulation and cell-based formal verification have limitations; SPICE offers circuit-level accuracy

Read More

Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design

Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design
by Admin on 11-05-2024 at 4:21 pm

The semiconductor industry is rapidly adopting 2.5D and 3D multi-die designs as the significant benefits have become clear for applications like HPC, GPU, mobile, and AI/ML. Multi-die design technology has been quickly evolving with early experiences leading to the development of more advanced implementation and analysis… Read More


Optical Scattering Measurements and Instruments Info Day

Optical Scattering Measurements and Instruments Info Day
by Admin on 11-04-2024 at 3:25 am

Overview

Learn the latest on Synopsys’ optical scattering measurement solutions.

During the event, you will have the opportunity to network with Synopsys experts, listen to technical talks, and see several demonstrations of our scattering measurement equipment

Agenda

Morning

Topics include:

  • General Overview of Synopsys
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Synopsys’ 30th Annual Test & SLM Special Interest Group (SIG) & International Test Conference (ITC)

Synopsys’ 30th Annual Test & SLM Special Interest Group (SIG) & International Test Conference (ITC)
by Admin on 11-04-2024 at 3:22 am

All members of the design and test community are invited to register to attend Synopsys’ 30th Annual Test & SLM Special Interest Group (SIG) at the 2024 International Test Conference (ITC).

The event will host experts from leading companies who will share how Synopsys Test and SLM solutions including AI-driven test, distributed… Read More


Webinar: Efficient and Robust Memory Verification in Modern SoCs Using Formal Equivalence Checker

Webinar: Efficient and Robust Memory Verification in Modern SoCs Using Formal Equivalence Checker
by Admin on 10-20-2024 at 6:05 pm

With the increasing complexity and importance of memories in modern ICs, there is a clear need for specialized tools and techniques for the design and verification of embedded memory blocks. Traditional methods like SPICE simulation and cell-based formal verification have limitations; SPICE offers circuit-level accuracy

Read More