Webinar: Marvell: Accelerating Interposer Design with Early Signal Integrity Analysis

Webinar: Marvell: Accelerating Interposer Design with Early Signal Integrity Analysis
by Admin on 04-09-2026 at 7:32 pm

In this webinar, Marvell will present how its team accelerates passive interposer routing for advanced 2.5D/3.5D multi die designs by bringing early, physics based signal integrity feedback into each routing iteration. Rather than relying on repeated, compute intensive 3D FEM cycles during development, Marvell uses a Method… Read More


Webinar: Powering 3D Multi-Die Designs with RedHawk-SC Electrothermal

Webinar: Powering 3D Multi-Die Designs with RedHawk-SC Electrothermal
by Admin on 04-08-2026 at 12:53 pm

As semiconductors continue to scale, designers are turning to 3DIC architectures to meet increasing demands for performance, energy efficiency, and functional density in data centers and edge AI applications. However, stacking multiple dies introduces new multiphysics challenges including electrical, structural, and… Read More


From SoC to System-in-Package: Transforming Automotive Compute with Multi-Die Integration

From SoC to System-in-Package: Transforming Automotive Compute with Multi-Die Integration
by Daniel Nenni on 04-08-2026 at 10:00 am

Types of Mutli Deisgn Packaging Synsopsys

Modern automotive electronics are undergoing a rapid transformation driven by increasing compute demands, functional safety requirements, and the shift toward scalable semiconductor architectures. One of the most significant technological developments enabling this transformation is the adoption of multi-die system… Read More


Webinar: Understanding UALink Architecture: A Protocol Deep Dive

Webinar: Understanding UALink Architecture: A Protocol Deep Dive
by Admin on 03-31-2026 at 11:55 pm

As AI workloads scale into the thousands of accelerators and hundreds of terabytes of distributed memory, traditional interconnects cannot deliver the deterministic latency, bandwidth efficiency, or memory semantic operations required for modern training clusters. UALink provides a purpose built accelerator fabric

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RISC-V Now! — Where Specification Meets Scale!

RISC-V Now! — Where Specification Meets Scale!
by Daniel Nenni on 03-31-2026 at 8:00 am

RVN! 26 SemiWiki (400 x 400 px) (1)

In forty plus years as a semiconductor professional I have never seen a semiconductor design ecosystem build as fast and as strong as RISC-V. As a result, RISC-V Now! has emerged as a pivotal gathering, a conference with a clear and ambitious mission: To transform the open, modular, and flexible RISC-V ISA from an exciting specificationRead More


Post-Silicon Validating an MMU. Innovation in Verification

Post-Silicon Validating an MMU. Innovation in Verification
by Bernard Murphy on 03-25-2026 at 6:00 am

Innovation New

Some post-silicon bugs are unavoidable, but we’re getting better at catching them before we ship. Here we look at a method based on a bare-metal exerciser to stress-test the MMU. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More


Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces

Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces
by Kalar Rajendiran on 03-23-2026 at 10:00 am

Bump maps for HBM PHY and HBM memory

This article concludes the three-part series examining key methodologies required for successful multi-die design. The first article Reducing Risk Early: Multi-Die Design Feasibility Exploration focused on feasibility exploration and early architectural validation, while the second article Building the InterconnectRead More


Agentic AI and the Future of Engineering

Agentic AI and the Future of Engineering
by Daniel Nenni on 03-13-2026 at 6:00 am

sassine announces agentic ai hires converge 2026

Agentic AI emerges in this Synopsys Converge keynote not as a futuristic add-on, but as a practical response to the growing complexity of engineering. In the speaker’s view, the traditional way of designing chips, systems, and intelligent products is no longer sufficient for the era of physical AI. Engineers are now dealing with… Read More


Efficient Bump and TSV Planning for Multi-Die Chip Designs

Efficient Bump and TSV Planning for Multi-Die Chip Designs
by Daniel Nenni on 03-10-2026 at 6:00 am

Efficient Bump and TSV Planning for Multi Die Chip Designs

The semiconductor industry has experienced rapid advancements in recent years, particularly with the increasing demand for high-performance computing, artificial intelligence, and advanced automotive systems. Traditional single-die chip designs are often unable to meet modern PPA requirements. As a result, engineers… Read More


Reducing Risk Early: Multi-Die Design Feasibility Exploration

Reducing Risk Early: Multi-Die Design Feasibility Exploration
by Kalar Rajendiran on 03-05-2026 at 10:00 am

Feasibility Thermal Map

The semiconductor industry is entering a new era in system design. As traditional monolithic scaling approaches its economic and physical limits, multi-die architectures are emerging as a primary pathway for delivering continued improvements in performance, power efficiency, and integration density. By distributing … Read More