In a rapidly evolving semiconductor landscape, where AI demands unprecedented computational power and efficiency, Synopsys has deepened its partnership with TSMC to pioneer advancements in AI-driven designs and multi-die systems. Announced during the TSMC OIP Ecosystem Summit last week, this collaboration leverages … Read More
Tag: synopsys
AI Everywhere in the Chip Lifecycle: Synopsys at AI Infra Summit 2025
At the AI Infra Summit 2025, Synopsys showed how artificial intelligence has become inseparable from the process of creating advanced silicon. The company’s message was clear: AI is an end-to-end engine that drives every phase of chip development. Three Synopsys leaders illustrated this from distinct vantage points. Godwin… Read More
Webinar: ML-Enhanced TCAD Calibration With 10x Reduction in Time to Results
Date: Oct 15, 2025 | 5:00 PM PST
Featured Speakers:
- Saurabh Suryavanshi, Product Manager, Synopsys
- Youngkwon Cho, Senior Staff Engineer, Synopsys
- Dipanjan Basu, Principal Engineer, Synopsys
Calibration is an essential part of enabling TCAD products usages inside Semiconductor fab. Synopsys has been leading the development
Synopsys Collaborates with TSMC to Enable Advanced 2D and 3D Design Solutions
Synopsys has deepened its collaboration with TSMC certifying the Ansys portfolio of simulation and analysis tools for TSMC’s cutting-edge manufacturing processes including N3C, N3P, N2P, and A16. This partnership empowers chip designers to perform precise final checks on designs, targeting applications in AI acceleration,… Read More
The Impact of AI on Semiconductor Startups
At the AI Infra Summit 2025 was a panel conversation that captured the semiconductor industry’s anxieties and hopes. The session, titled “The Impact of AI on Semiconductor Startups,” examined how artificial intelligence is transforming not just what chips can do, but how we design them.
The backdrop is stark. Developing a leading-edge… Read More
Webinar: IP Design Considerations for Real-Time Edge AI Systems
*Work Email Required*
Edge AI systems increasingly require on-chip integration of large-capacity memory, compute engines, and inference-optimized accelerators—all within strict power, latency, and footprint constraints. This webinar provides a an overview of IP architecture and integration methodologies that support… Read More
Synopsys Announces Expanding AI Capabilities and EDA AI Leadership
In the fast-paced semiconductor industry Synopsys has redefined EDA with its Synopsys.ai Copilot, a generative AI tool. Since its launch in November 2023, and yes I was at the launch and very skeptical, Copilot has evolved to address the industry’s growing design complexity and projected 15-30% workforce gap by 2030. Let’s… Read More
The Rise, Fall, and Rebirth of In-Circuit Emulation (Part 1 of 2)
Introduction: The Historical Roots of Hardware-Assisted Verification
The relentless pace of semiconductor innovation continues to follow an unstoppable trend: the exponential growth of transistor density within a given silicon area. This abundance of available semiconductor fabric has fueled the creativity of design… Read More
Webinar: Why Choose PCIe 5.0 for Power, Performance, and Bandwidth at the Edge?
Featured Speakers:
- Gustavo Pimentel, Principal Product Marketing Manager, Synopsys
As edge, mobile and automotive applications demand faster data processing, lower latency, and reduced power consumption, PCI Express® 5.0 has emerged as the optimal interconnect standard. Doubling the data rate of PCIe 4.0 while enabling
Webinar: Static Verification of RTL DFT Connectivity – Getting it Right the First Time!
Featured Speakers:
- Kiran Vittal, Synopsys
- Ayush Goyal, Synopsys
As System-on-Chip (SoC) designs become increasingly complex, ensuring reliable Design-for-Test (DFT) connectivity at the RTL stage is more important than ever. This Synopsys webinar will demonstrate how static verification techniques, powered by TestMAX™