Avestra: Agentic AI for SystemVerilog Assertion Generation

Avestra: Agentic AI for SystemVerilog Assertion Generation
by Daniel Nenni on 08-24-2026 at 2:00 pm

Avestra Studio Tuple Tech

Modern ASIC, SoC, CPU, and GPU development depends on verification processes that detect subtle functional defects before tapeout. SystemVerilog Assertions (SVA) are particularly important because they encode temporal design intent: how signals, states, and transactions must behave across clock cycles. Unlike conventional… Read More


Webinar: Shift Left to Ship Faster: Verifying IP and SoCs at Real Workload Speeds

Webinar: Shift Left to Ship Faster: Verifying IP and SoCs at Real Workload Speeds
by Admin on 08-20-2026 at 11:40 pm

Featured Speakers:

  • Madhumita Sanyal, Sr. Director of Technical Product Management, Synopsys
  • Varun Agrawal, Director of Product Management, Synopsys

As SoC complexity climbs, traditional verification can’t keep pace — and system-level bugs surface late, when they’re hardest to fix. By pairing Hardware-Assisted… Read More


Meet Quadric on the Road: Three Must-Attend AI Events

Meet Quadric on the Road: Three Must-Attend AI Events
by Daniel Nenni on 08-19-2026 at 6:00 am

Catch Quadric Hot Chips AI Infra

This late summer, Quadric is taking its vision for programmable, on-device AI to three of the industry’s most influential gatherings. From advanced processor design at HotChips to scalable deployment at the AI Infra Summit and physical AI at Embedded World North America, each stop offers a different opportunity to see how the… Read More


Webinar: Cutting Full-Chip SoC Debug from Days to Minutes with AI

Webinar: Cutting Full-Chip SoC Debug from Days to Minutes with AI
by Admin on 08-17-2026 at 3:51 pm

COMPANY EMAIL REQUIRED FOR REGISTRATION

Full-chip SoC debug has become one of the most expensive bottlenecks in modern verification. A single production issue can pull multiple engineers away days as they chase a failure through waveforms, logs, and across hundreds of thousands of lines of code.

In this webinar, we will demonstrate… Read More


ESD Alliance Webinar: Gen-AI for Chip Design and Security

ESD Alliance Webinar: Gen-AI for Chip Design and Security
by Admin on 08-03-2026 at 7:27 pm

This webinar will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification.

Designing functionally correct, high-performance, and provably secure system-on-chips (SoCs) has become a strategic imperative for modern computing infrastructure. Yet traditional… Read More


Webinar: Defacto is Boosting Front-end SoC Design With AI-Powered EDA tools

Webinar: Defacto is Boosting Front-end SoC Design With AI-Powered EDA tools
by Admin on 06-29-2026 at 9:22 pm

**Please register with professional email address**

As SoC design complexity grows and design windows shrink, EDA tools must evolve beyond traditional workflows. AI is the catalyst!

This webinar explores what the next generation of EDA tools and design platforms should look like when built with AI in the middle. We’ll… Read More


Webinar: Defacto is Boosting Front-end SoC Design With AI-Powered EDA tools

Webinar: Defacto is Boosting Front-end SoC Design With AI-Powered EDA tools
by Admin on 06-26-2026 at 11:14 am

**Please register with professional email address**

As SoC design complexity grows and design windows shrink, EDA tools must evolve beyond traditional workflows. AI is the catalyst!

This webinar explores what the next generation of EDA tools and design platforms should look like when built with AI in the middle. We’ll… Read More


Chips&Media’s Next-Generation Video CODEC IP Powers Ambarella’s Expanding Edge AI Portfolio

Chips&Media’s Next-Generation Video CODEC IP Powers Ambarella’s Expanding Edge AI Portfolio
by Daniel Nenni on 06-15-2026 at 8:00 am

image (11)

Chips&Media has announced a strategic licensing agreement with Ambarella for its latest-generation video CODEC intellectual property (IP), marking a significant milestone in the evolution of edge AI, computer vision, and physical AI systems. The agreement follows an extensive technical evaluation process and further… Read More


How llmda.ai Coaxed Me Out of Retirement, an Interview with Kurt Shuler

How llmda.ai Coaxed Me Out of Retirement, an Interview with Kurt Shuler
by Daniel Nenni on 06-12-2026 at 6:00 am

Kurt Shuler

Arteris is one of the most impressive companies SemiWiki has worked with over the last fifteen years. We have collaborated on one hundred and seventy-three articles/podcasts that have garnered more than two million views/listens. The success of Arteris can be easily tracked to the executive team and Kurt Shuler was the executive… Read More


CEO Interview with Geoffrey Rodgers of Chameleon Semiconductor

CEO Interview with Geoffrey Rodgers of Chameleon Semiconductor
by Daniel Nenni on 05-03-2026 at 2:00 pm

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Geoffrey Rodgers spent most of his career at the intersection of semiconductor technology and go-to-market execution, with a focus on scaling businesses and bringing complex solutions to market. He previously led the Analog Go-To-Market motion at Synopsys following the acquisition of Analog Design Automation and held leadership… Read More