Chips&Media’s Next-Generation Video CODEC IP Powers Ambarella’s Expanding Edge AI Portfolio

Chips&Media’s Next-Generation Video CODEC IP Powers Ambarella’s Expanding Edge AI Portfolio
by Daniel Nenni on 06-15-2026 at 8:00 am

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Chips&Media has announced a strategic licensing agreement with Ambarella for its latest-generation video CODEC intellectual property (IP), marking a significant milestone in the evolution of edge AI, computer vision, and physical AI systems. The agreement follows an extensive technical evaluation process and further… Read More


How llmda.ai Coaxed Me Out of Retirement, an Interview with Kurt Shuler

How llmda.ai Coaxed Me Out of Retirement, an Interview with Kurt Shuler
by Daniel Nenni on 06-12-2026 at 6:00 am

Kurt Shuler

Arteris is one of the most impressive companies SemiWiki has worked with over the last fifteen years. We have collaborated on one hundred and seventy-three articles/podcasts that have garnered more than two million views/listens. The success of Arteris can be easily tracked to the executive team and Kurt Shuler was the executive… Read More


CEO Interview with Geoffrey Rodgers of Chameleon Semiconductor

CEO Interview with Geoffrey Rodgers of Chameleon Semiconductor
by Daniel Nenni on 05-03-2026 at 2:00 pm

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Geoffrey Rodgers spent most of his career at the intersection of semiconductor technology and go-to-market execution, with a focus on scaling businesses and bringing complex solutions to market. He previously led the Analog Go-To-Market motion at Synopsys following the acquisition of Analog Design Automation and held leadership… Read More


Scalable Network-on-Chip Enables a Modular Chiplet Platform

Scalable Network-on-Chip Enables a Modular Chiplet Platform
by Daniel Nenni on 04-27-2026 at 10:00 am

MOSAICS Block Diagram

The semiconductor industry is undergoing a profound transformation as system complexity, performance expectations, and time-to-market pressures continue to rise. Traditional monolithic system-on-chip (SoC) designs are increasingly giving way to modular, chiplet-based architectures that enable flexibility, scalability,… Read More


Webinar: Cutting Full-Chip SoC Debug from Days to Minutes with AI

Webinar: Cutting Full-Chip SoC Debug from Days to Minutes with AI
by Admin on 04-25-2026 at 1:14 am

*Company Email Required for Registration*

Full-chip SoC debug has become one of the most expensive bottlenecks in modern verification. A single production issue can pull multiple engineers away days as they chase a failure through waveforms, logs, and across hundreds of thousands of lines of code.

In this webinar, we will demonstrate… Read More


Hardening the Silicon: Why Analog Anti-Tamper IP is the New Security Baseline

Hardening the Silicon: Why Analog Anti-Tamper IP is the New Security Baseline
by Daniel Nenni on 04-14-2026 at 10:00 am

Agile Analog security image

In today’s increasingly connected world, there are billions of SoCs, powering everything from automotive ECUs to industrial IoT sensors and processing sensitive data. While software-level security is taken seriously, hardware-level vulnerabilities have often been an afterthought. As hackers are now using more complex… Read More


NoC Matters: Designing the Backbone of Next-Gen AI SoCs

NoC Matters: Designing the Backbone of Next-Gen AI SoCs
by Daniel Nenni on 04-13-2026 at 10:00 am

Arteris NoC Hardware

Modern SoC design for artificial intelligence workloads has fundamentally shifted the role of the network-on-chip (NoC) from a simple connectivity fabric to a primary architectural determinant of system performance, power, and scalability. As compute density increases and heterogeneous accelerators proliferate, data… Read More


Hardware is the Center of the Universe (Again)

Hardware is the Center of the Universe (Again)
by Lauro Rizzatti on 02-23-2026 at 10:00 am

Hardware is the Center of the Universe (Again) Figure 1

The 40-Year Evolution of Hardware-Assisted Verification — From In-Circuit Emulation to AI-Era Full-Stack Validation

For more than a decade, Hardware-Assisted Verification platforms have been the centerpiece of the verification toolbox. Today, no serious semiconductor program reaches tapeout without emulation or FPGA-prototyping… Read More


Verification Futures Conference 2026 UK

Verification Futures Conference 2026 UK
by Admin on 01-13-2026 at 6:17 pm

Verification Futures UK 2026, co-located with Semiconductors Futures 2026 organised by Tessolve and co-organised this year with Alpinum. The conference continues its strong tradition of delivering a unique blend of conference presentations, exhibitions, training, and industry networking sessions focused on the challenges… Read More


TSMC based 3D Chips: Socionext Achieves Two Successful Tape-Outs in Just Seven Months!

TSMC based 3D Chips: Socionext Achieves Two Successful Tape-Outs in Just Seven Months!
by Daniel Nenni on 12-31-2025 at 6:00 am

Synopsys Socionext 3d IC

Socionext’s recent run of rapid 3D-IC tape-outs is a noteworthy milestone for the industry with two successful tape-outs in just seven months for complex, multi-die designs aimed at AI and HPC workloads. That pace of iteration highlights how advanced packaging, richer EDA toolchains, and closer foundry-ecosystem collaboration… Read More