One FPGA synthesis flow for different IP types

One FPGA synthesis flow for different IP types
by Don Dingee on 05-06-2016 at 4:00 pm

Both Altera and Xilinx are innovative companies with robust ecosystems, right? It would be a terrible shame if you located the perfect FPGA IP block for a design, but couldn’t use it because it was in the “wrong” format for your preferred FPGA. What if there were a way around that?

There is a compelling argument to use each FPGA vendor’s… Read More


Got FPGA Timing Closure Problems?

Got FPGA Timing Closure Problems?
by Paul McLellan on 02-26-2015 at 7:00 am

I had a meeting with Harn Hua Ng, the CEO of Plunify, a couple of weeks ago. They are an EDA company that I’d never heard of. Partially that is because they only play in the FPGA space, a country I visit less frequently than SoC land. Plus, they are based in Singapore, a country I have only been to a couple of times in my life.

Plunify… Read More


Next Generation Remote Access: Under the Hood

Next Generation Remote Access: Under the Hood
by Paul McLellan on 08-16-2013 at 2:56 pm

I wrote a few weeks ago about Zentera’s push to create a new standard for remote access that allows semiconductor companies and EDA companies to cooperate on resolving issues without requiring that the semiconductor company’s IP leaves the company network. At the 50,000 foot level, Zentera’s technology … Read More


Do you need more machines? Licenses? How can you find out?

Do you need more machines? Licenses? How can you find out?
by Paul McLellan on 04-26-2012 at 9:00 pm

Do you need more servers? Do you need more licenses? If you are kicking off a verification run of 10,000 jobs on 1,000 server cores then you are short of 9000 cores and 9000 licenses, but you’d be insane to rush out with a purchase order just on that basis. Maybe verification isn’t even on the critical path for your design,… Read More