As RF systems continue to evolve with wider bandwidths and higher frequencies, engineers are navigating faster plays, tighter margins, and more complex signals than ever before. The challenge is no longer capturing signals, it is turning those measurements into meaningful… Read More
As RF systems continue to evolve with wider bandwidths and higher frequencies, engineers are navigating faster plays, tighter margins, and more complex signals than ever before. The challenge is no longer capturing signals, it is turning those measurements into meaningful insights that accelerate design and validation.… Read More
Hosted in collaboration with Professor Slim Boumaiza, Director of the Centre for Intelligent Antenna and Radio Systems (CIARS) at the University of Waterloo.
As RF systems continue to evolve with wider bandwidths and higher frequencies, engineers are navigating faster plays, tighter margins, and more complex signals than… Read More
The Semiconductor Seminar 2026 is coming to Monterrey, bringing together engineers, researchers, and industry professionals to explore practical approaches to device design, modeling, characterization, validation, testing, and safety.
Through expert-led sessions and live demonstrations, you will
What: Better IP Test with IJTAG
When: 26 March, 2013, 10:30am-1:30pm
Where: Mentor Graphics, 46871 Bayside Parkway, Fremont, CA 94538
If you are involved in IC test*, you’ve probably heard about the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG. IJTAG defines a standard for embedded IP that includes simple… Read More
Last week I attended the Ansys/Apache seminars on “Dimensions of Electronic Design.” The two big challenges as we go down to 28nm and 20nm and below are keeping power manageable and keeping reliability up.
The big challenge with power is that we can put so much stuff on a die and clock it so fast that the power is exceeding… Read More
If you are involved in testing memory or logic of ARM-based designs, you’ll want to attend this free seminar on July 17, 2012 in Santa Clara. Mentor Graphics and ARM have a long standing partnership, and have optimized the Mentor test products (a.k.a Tessent) for the ARM processors and memory IP.
The lunch seminar runs from 10:30-1:00… Read More
Jasper has three seminars coming up in May in Hsinchu (Taiwan), Beijing and Shanghai. These are full-day seminars on how to solve critical verification challenges using state-of-the-art formal technology. Breakfast and lunch will be served.
This full-day tutorial will be given by technical experts for verification experts… Read More
Atrenta has four seminars coming up on SoC realization. More and more design is actually about finding IP and integrating it together at the block level, and then handing it off to a standard RTL to GDSII flow. The three focus areas are:
