Board Design & System Analysis Update Seminar 2024

Board Design & System Analysis Update Seminar 2024
by Admin on 12-26-2023 at 8:19 pm

Date and time: February 2, 2024 (Friday) 13:00-14:40

Sponsor:

Japan Cadence Design Systems
Innotek Co., Ltd. IC Solution Headquarters

Cost: Free

Venue: Online (Zoom webinar)

*You can also participate from a web browser.

We recommend using Google Chrome, Firefox, or Chromium Edge.

Registration deadline: February 1st (Thursday)… Read More


Speed, Protocol and Security: New Automotive Network Challenges

Speed, Protocol and Security: New Automotive Network Challenges
by Admin on 12-18-2023 at 8:43 pm

Agenda Timeline: 10:30 a.m. – 1:00 p.m.
Registration Time: 10:00 a.m.
Lunch will be provided

What this event is about:

Validate your in-vehicle network (IVN) performance to ensure flawless data flow between on-board sensors and electronic control units. To ensure optimal design, functionality, performance, safety,… Read More


2023 Cadence China Technology Tour Seminar

2023 Cadence China Technology Tour Seminar
by Admin on 11-15-2023 at 2:26 pm

Digital Design and Signoff Seminar

Conference introduction

Cadence, a leading supplier in the field of electronic design automation, sincerely invites you to participate in the “2023 Cadence China Technology Tour Seminar”. The conference will bring together Cadence developers and senior technical experts

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HLS Design and Verification Seminar 2023 

HLS Design and Verification Seminar 2023 
by Admin on 11-07-2023 at 4:23 pm

We will be holding a high-level synthesis technical forum. The past few years have been held online, but this year we were able to return to the venue. We have prepared a variety of proposals, including success stories and new technology updates related to high-level design and verification, so please come and join us, even if

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Stratus HLS (High Level Synthesis) Seminar Series: [Part 5] Verification of high-level synthesis RTL and Stratus integration flow

Stratus HLS (High Level Synthesis) Seminar Series: [Part 5] Verification of high-level synthesis RTL and Stratus integration flow
by Admin on 10-04-2023 at 5:11 am

Date and time: Friday, November 10, 2023 15:00-16:00

Sponsor: Japan Cadence Design Systems, Innotek Co., Ltd. IC Solution Headquarters

Cost: Free

Venue: Online (Zoom webinar)

*You can also participate from a web browser.

We recommend using Google Chrome, Firefox, or Chromium Edge.

Registration deadline: November 9th (Thursday)

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CadenceCONNECT: IR2.0 – Building a New Paradigm for Power Integrity Design and Analysis

CadenceCONNECT: IR2.0 – Building a New Paradigm for Power Integrity Design and Analysis
by Admin on 10-04-2023 at 5:04 am

Date: November 2, 2023

Time: 10:00am – 5:00pm

Location: Cadence Headquarters, San Jose, CA | Building 10 – Auditorium

Power integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding

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