NewPath Research will describe their new method for nanoscale carrier profiling in semiconductors on May 19[SUP]th[/SUP] at the Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) in Saratoga Springs, NY. This new method is intended to fill the gap that has been addressed in the Roadmaps for the semiconductor… Read More
Tag: semieda
Aldec is Celebrating 30 Years @ #51DAC!
Dr. Stanley Hyduke founded Aldec in 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Today, Aldec … Read More
IP Reuse and Management in Monterey!
One of the benefits of being part of SemiWiki is building relationships with a wide variety of companies covering every semiconductor design application imaginable. We are blessed, absolutely. Another benefit of being part of SemiWiki are the invitations to attend, participate, and even organize events such as EDPS. Last year… Read More
The CAD Team – Unsung Heroes in a Successful Tapeout
For most of my career, I worked as a CAD and design flow engineer. In the fall of 2012, I moved to a different role, as an applications and support manager at ClioSoft Inc. In my opinion, this was a very good opportunity for me to work with other CAD engineers and teams.
Having worked with different CAD teams in my career, I have often felt… Read More
Verifying DRC Decks and Design Rule Specifications
DRVerify is part of the iDRM design rule compiler platform from Sage DA, something that I have been personally involved with for the past three years. DRVerify is mainly used to verify third party design rule check (DRC) decks and ensure that they correctly, completely and accurately represent the design rule specification. In… Read More
Intel 14nm Delayed Again?
From the sources in which I confirmed the last Intel 14nm delay, I just confirmed another. Intel 14nm is STILL having yield problems. Remember Intel bragging about 14nm being a full node and deriding TSMC because 16nm is “just” 20nm with FinFETs added? Judging by the graph, clearly FinFETs are not the problem here. … Read More
Cliosoft Grows Again!
Cliosoft was one of the first companies to work with SemiWiki so they are an integral part of our amazing growth and we are part of theirs. I remember talking to Srinath Anantharaman (Cliosoft CEO) for the first time and discussing the goals of working together. It was simple really, there was disinformation in the market about Cliosoft… Read More
Why Intel 14nm is NOT a Game Changer!
On one hand the Motley Fool is saying, “Intel 14nm could change the game” and on the other hand the Wall Street Cheat Sheet is saying, “Intel should shut down mobile”. SemiWiki says Intel missed mobile and should look to the future and focus on wearables and in this blog I will argue why.
Let’s look back to 2009 when Intel and TSMC signed… Read More
Cadence Design Systems’ Shares Are Surprisingly Cheap
In the third and final (for now) part of this series on the EDA design tool vendors, I’d like to take a closer look at Cadence Design Systems. This is probably the most interesting of the three from both an industry perspective as well as an investment perspective for a variety of reasons. With that said I’d like to first provide some … Read More
Analog & Mixed-Signal Design Lunch & Learn
I’m a big fan of lunch and learns, mainly because I’m a big fan of lunch but I also like to learn. I’m also a big fan of Tanner EDA which is why I helped organize this event. Face to face interaction amongst the fabless semiconductor ecosystem is critical to our success so stop on by and network, lunch is on me.
Take a look at the Brief History… Read More