1964 Vision, Volume and Moore’s Law
The 1964 New York World’s Fair saw Lee Iacocca, then a young 40 year old General Manager, introduce a car that inspired “total performance” and was for a “young America out to have a good time.” This young America would become the baby boomer generation. The Mustang was revolutionary in its affordability,… Read More
Tag: semiconductors
GlobalFoundries and IBM
So it’s true. IBM is selling its semiconductor division to GlobalFoundries. Actually, selling is a sort of euphemism for paying them $1.5B to take it off their hands. At least according to Bloomberg. There have been rumors for weeks that IBM wanted to pay $1B to get rid of the division, but GF wanted $2B. Looks like they split… Read More
Is Number of Signoff Corners an Issue?
Semiconductor companies continue to use the traditional corner-based signoff approach that has been developed more than 40+ years ago and has since remained mainly unchanged as an industry paradigm. Initially it had 2 corners, namely Worst Case (WC) and Best Case (BC) with the maximum and minimum cell delay respectively. Note… Read More
GlobalFoundries on the Road
Every year in the fall GlobalFoundries has a series of technical seminars they take on the road around the US. This year it kicks off on Tuesday, October 21 at the Doubletree Hotel in San Jose. Two days later it is at Dana Point (southern CA) and on the 30th it goes to Austin (you don’t need me to tell you where Austin is, I’m… Read More
EDA Plus ARM Equals Big Views!
In looking at the SemiWiki analytics, one of the top search terms that brings traffic to our site is ARM, just about anything ARM. In fact, that’s what the next SemiWiki book will be about. Yes, ARM is that interesting. While EDA is also one of our top search terms, EDA+ARM will get the most views, absolutely. And let’s face it, bloggers… Read More
How to detect weak nodes in a power-off analog circuit?
Most analog cells have a power off mode intended to reduce power consumption. In this mode, all the circuit branches between the supply lines are set in a high impedance mode by driving MOS gates to a blocking voltage. This is a somewhat similar situation to that in tri-state digital circuits.
When a branch is set in that high impedance… Read More
Do you check your circuit DC stability?
Most analog designers are aware of loops stability. In most cases, stability is understood as AC stability, the goal is ensuring enough phase (gain) margin so as to avoid the loop to enter oscillation. But prior to studying AC stability, DC stability should be questioned. What is that DC stability only few people think of?… Read More
Distributed RLCK Models for Transmission Lines in High Speed Applications
Design engineers frequently struggle with transmission line design and modeling. We can define a length of interconnect that contains more than 1/100th of a wavelength as a transmission line. This seems to be the breakpoint where distributed effects to start to become significant. To improve circuit performance these long … Read More
The Great 28nm Debacle!
40nm was a big node while I was Director of Foundries at the IP company Virage Logic which was later acquired by Synopsys. 40nm was big because the top fabless companies multi-sourced designs from one foundry to another with relative ease to get the best wafer prices. It was also the node where some of the big IDMs went fab-lite moving… Read More
Mentor Graphics @ SEMICON West 2014
Mentor is again the most represented EDA company at SEMICON West this year. I strongly advise Cadence and Synopsys to get more involved because EDA may be where electronics begins but semiconductor manufacturing makes all of our hard work come true, absolutely. Paul McLellan, Beth Martin, and I will be blogging live, I hope to see… Read More