Leveraging Common Weakness Enumeration (CWEs) for Enhanced RISC-V CPU Security

Leveraging Common Weakness Enumeration (CWEs) for Enhanced RISC-V CPU Security
by Kalar Rajendiran on 05-13-2025 at 6:00 am

Information Flow Analysis Cycuity's Unique Approach

As RISC-V adoption accelerates across the semiconductor industry, so do the concerns about hardware security vulnerabilities that arise from its open and highly customizable nature. From hardware to firmware and operating systems, every layer of a system-on-chip (SoC) design must be scrutinized for security risks. Unlike… Read More


CEO Interview with Richard Hegberg of Caspia Technologies

CEO Interview with Richard Hegberg of Caspia Technologies
by Daniel Nenni on 05-02-2025 at 6:00 am

Richard Hegberg

Rick has a long and diverse career in the semiconductor industry. He began as VP of sales at Lucent Microelectronics. He has held executive roles at several high-profile companies and participated in several acquisitions along the way. These include NetApp, SanDisk/WD, Atheros/Qualcomm, Numonyx/Micron, ATI/AMD, and VLSI… Read More


Innovation in Verification – February 2020

Innovation in Verification – February 2020
by Bernard Murphy on 02-11-2020 at 6:00 am

Innovation in Verification

This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea in verification and debate its strengths and opportunities for improvement.

Our goal is to support and appreciate further innovation in this area. Please let us know what you think and please… Read More


Security and RISC-V

Security and RISC-V
by Bernard Murphy on 11-30-2018 at 7:00 am

One of the challenges in the RISC-V bid for world domination may be security. That may seem like a silly statement, given that security weaknesses are invariably a function of implementation and RISC-V doesn’t define implementation, only the instruction-set architecture (ISA). But bear with me. RISC-V success depends heavily… Read More