Tag: rtl partitioning

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Conquering errors in the hierarchy of FPGA IP

Conquering errors in the hierarchy of FPGA IP
by Don Dingee on 12-02-2013 at 10:00 am
Categories: EDA, Synopsys

FPGA design today involves not only millions of gates on the target device, but thousands of source files with RTL and constraints, often generated by multiple designers or third party IP providers. With modules organized in some logical way describing the design, designers brace themselves for synthesis and a possible avalanche… Read More

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More to the story than bigger FPGA-based prototyping

More to the story than bigger FPGA-based prototyping
by Don Dingee on 08-19-2013 at 5:00 pm
Categories: EDA, FPGA, Synopsys

Still not convinced on the value of FPGA-based prototyping systems, or using older technology? I’ve been trying to find the story beyond just bigger, badder FPGAs in a box that you pour RTL into – and found some hints in a webinar on the Synopsys HAPS-70 from earlier this year.… Read More