Mentor gets Busy at DVCon

Mentor gets Busy at DVCon
by Bernard Murphy on 02-20-2017 at 12:00 pm

You’d expect Mentor to be covering a lot of bases at DVCon and you wouldn’t be wrong. They’re hosting tutorials, a lunch, papers, posters, there’s a panel and of course they’ll be on the exhibit floor. I’ll start with an important tutorial that you really should attend, Monday morning, on creating Portable Stimulus Models… Read More


When Good Standards Get Lost – the UVM Register Model

When Good Standards Get Lost – the UVM Register Model
by Bernard Murphy on 01-20-2016 at 12:00 pm

Some time ago I wrote a DeepChip viewpoint on DVCON 2014 in which I praised a Mentor paper “Of Camels and Committees”. The authors argued that while the UVM standards committee had a done a great job in the early releases, the 1.2 release was overloaded with nice-to-have features with questionable value for a standard, particularly… Read More


Never Imagined So Easy Class-based Testbench Debugging

Never Imagined So Easy Class-based Testbench Debugging
by Pawan Fangaria on 08-09-2015 at 7:00 am

When it comes to debugging a design testbench organized in object-oriented style with objects, component hierarchies, macros, transactions and so on, it becomes an onerous, tasteless, and thankless task for RTL verification engineers who generally lag in software expertise. Moreover, class-based debugging tools have lagged… Read More