Are Standard Cell Libs, Memories and Mixed-signal IP Availabe at 7nm FF?

Are Standard Cell Libs, Memories and Mixed-signal IP Availabe at 7nm FF?
by Eric Esteve on 05-05-2016 at 7:00 am

More than 500 designers (562) have responded to a survey made in 2015 by Synopsys. Answering to the question “What is the fastest clock speed of your design?” 56% have mentioned a clock higher than 500 MHz (and still 40% higher than 1 GHz). If you compare with the results obtained 10 years ago, the largest proportion of answers was for… Read More


PCI Express 4 specification just released for PCI-SIG DevCon

PCI Express 4 specification just released for PCI-SIG DevCon
by Eric Esteve on 07-01-2014 at 4:45 am

I have been alerted by a blog from Moshik Rubin from Cadence: PCI-SIG has finally released the PCIe 4.0 rev 0.3 specification for members’ review, on time for the PCI-SIG developers conference last June in Santa Clara. Since the early days of PCI Express in 2005, Denali (at that time, now Cadence) has positioned the PCIe VIP… Read More