Predicting Bugs: ML and Static Team Up. Innovation in Verification

Predicting Bugs: ML and Static Team Up. Innovation in Verification
by Bernard Murphy on 06-11-2020 at 6:00 am

innovation

Can we predict where bugs are most likely to be found, to better direct testing? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, again through a paper in software verification we find equally relevant to hardware. Feel free to comment if you agree or disagree.

The InnovationRead More


Is Mutation Testing Worth the Effort? Innovation in Verification

Is Mutation Testing Worth the Effort? Innovation in Verification
by Bernard Murphy on 05-19-2020 at 6:00 am

innovation

Mutation testing is an intriguing idea, but is it useful? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, here looking at a paper examining the pros and cons of this topic. Feel free to comment if you agree or disagree.

The Innovation

This month’s pick is Which Software Read More


Innovation in Verification April 2020

Innovation in Verification April 2020
by Bernard Murphy on 04-14-2020 at 6:00 am

Innovation

This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea we appreciated and suggest opportunities to further build on that idea.

We’re getting a lot of hits on these blogs but would like really like to get feedback also.

The Innovation

Our next pick… Read More


Innovation in Verification March 2020

Innovation in Verification March 2020
by Bernard Murphy on 03-17-2020 at 6:00 am

Innovation

This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea we appreciated and suggest opportunities to further build on that idea.

We welcome comments on our blogs and suggestions for new topics if they’re based on published work.

The Innovation

Our… Read More


Innovation in Verification – February 2020

Innovation in Verification – February 2020
by Bernard Murphy on 02-11-2020 at 6:00 am

Innovation in Verification

This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea in verification and debate its strengths and opportunities for improvement.

Our goal is to support and appreciate further innovation in this area. Please let us know what you think and please… Read More


Innovation in Verification – January 2020

Innovation in Verification – January 2020
by Bernard Murphy on 01-09-2020 at 6:00 am

Innovation

I’m kicking off a blog series which should appeal to many of us in functional verification. Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan (angel investor and board member extraordinaire) and I (sometime blogger) like to noodle from time to time on papers and other verification articles which inspire us.… Read More


The ESD Alliance Welcomes You to an Evening with Jim Hogan and Paul Cunningham

The ESD Alliance Welcomes You to an Evening with Jim Hogan and Paul Cunningham
by Bob Smith on 04-05-2019 at 7:00 am

An informal “Fireside Chat” like no other featuring Jim Hogan, managing partner of Vista Ventures, LLC., and Paul Cunningham, Cadence’s corporate vice president and general manager of the system verification group, is in the works for Wednesday, April 10.

Hosted by the ESD Alliance, a SEMI Strategic Association Partner, at … Read More


Digital Design Trends – A Cadence Perspective

Digital Design Trends – A Cadence Perspective
by Bernard Murphy on 04-21-2016 at 7:00 am

I talked with Paul Cunningham (VP front-end digital R&D) at CDNLive recently to get a Cadence perspective on digital design trends. He sees needs from traditional semiconductor companies evolving as usual, with disruption here and there from consolidation. But on the system side there is explosion in demand – for wearables,… Read More


Cadence Adds New Dimension to SoC Test Solution

Cadence Adds New Dimension to SoC Test Solution
by Pawan Fangaria on 02-04-2016 at 7:00 am

It requires lateral thinking in bringing new innovation into conventional solutions to age-old hard problems. While the core logic design has evolved adding multiple functionalities onto a chip, now called SoC, the structural composition of DFT (Design for Testability) has remained more or less same based on XOR-based compression… Read More