The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)

The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)
by Lauro Rizzatti on 11-19-2024 at 10:00 am

Immensity of SW development Part 4 Table 1

The Impact of AI on Software and Hardware Development

Part 4 of this series analyzes how AI algorithmic processing is transforming software structures and significantly modifying processing hardware. It explores the marginalization of the traditional CPU architecture and demonstrates how software is increasingly dominatingRead More


The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)

The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)
by Lauro Rizzatti on 10-03-2024 at 10:00 am

Immensity of SW development Part 3 Figure 1

Part 3 of this 4-part series analyzes methods and tools involved in debugging software at different layers of the software stack.

Software debugging involves identifying and resolving issues ranging from functional misbehaviors to crashes. The essential requirement for validating software programs is the ability to monitor… Read More


The Immensity of Software Development the Challenges of Debugging (Part 1 of 4)

The Immensity of Software Development the Challenges of Debugging (Part 1 of 4)
by Lauro Rizzatti on 07-15-2024 at 10:00 am

Immensity of SW development Fig 1

Part 1 of this 4-part series introduces the complexities of developing and bringing up the entire software stack on a System on Chip (SoC) or Multi-die system. It explores various approaches to deployment, highlighting their specific objectives and the unique challenges they address.

Introduction

As the saying goes, it’s… Read More


Reduce Risk, Ensure Compliance: Hardware-Assisted Verification for Design Certification

Reduce Risk, Ensure Compliance: Hardware-Assisted Verification for Design Certification
by Lauro Rizzatti on 06-12-2024 at 10:00 am

Reduce risk ensure compliance Figure 1
Prologue

Peter was running late for two reasons. First, he encountered unexpected heavy traffic and arrived ten minutes late for a crucial meeting with a customer to run a compliance test of his new 6G phone design prototyped on FPGAs. This prototype’s success was pivotal, as it could secure a significant purchase order.Read More


SoC Power Islands Verification with Hardware-assisted Verification

SoC Power Islands Verification with Hardware-assisted Verification
by Lauro Rizzatti on 05-14-2024 at 10:00 am

SoC Power Islands Figure 1

The ever-growing demand for longer battery life in mobile devices and energy savings in general have pushed power optimization to the top of designers’ concerns. While various techniques like multi-VT transistors and clock gating offer power savings at gate-level design, the real impact occurs at system level, where hardware… Read More


DSP SoC a la Française

DSP SoC a la Française
by Lauro Rizzatti on 02-04-2018 at 11:00 am

I enjoyed reading Eric Esteve’s article “ French Tech at CES, 2nd country after USA with 274 Start-Up at Eureka Park!” It brought back happy memories of my time at EVE until Synopsys purchased it in 2012.Here is another intriguing story by a French startup named VSORA and founded by Khaled Maalej with a team of scientists and engineers.Read More


The Evolution of Emulation

The Evolution of Emulation
by Bernard Murphy on 06-13-2016 at 7:00 am

Mentor hosted a panel on emulation in their booth at DAC this year. One thing I really liked about this panel is that it didn’t include anyone from Mentor. Not that I have anything against Mentor employees, who are a fine bunch of people from those I know, but I find panels most interesting when the discussion is purely among customers.… Read More