Lessons from the DeepChip Wars: What a Decade-old Debate Teaches Us About Tech Evolution

Lessons from the DeepChip Wars: What a Decade-old Debate Teaches Us About Tech Evolution
by Lauro Rizzatti on 11-10-2025 at 10:00 am

Lessons from the DeepChip wars Table

The competitive landscape of hardware-assisted verification (HAV) has evolved dramatically over the past decade. The strategic drivers that once defined the market have shifted in step with the rapidly changing dynamics of semiconductor design.

Design complexity has soared, with modern SoCs now integrating tens of billions… Read More


Inference Acceleration from the Ground Up

Inference Acceleration from the Ground Up
by Lauro Rizzatti on 10-29-2025 at 6:00 am

VSORA AI CHip

VSORA, a pioneering high-tech company, has engineered a novel architecture designed specifically to meet the stringent demands of AI inference—both in datacenters and at the edge. With near-theoretical performance in latency, throughput, and energy efficiency, VSORA’s architecture breaks away from legacy designs optimized… Read More


The Rise, Fall, and Rebirth of In-Circuit Emulation: Real-World Case Studies (Part 2 of 2)

The Rise, Fall, and Rebirth of In-Circuit Emulation: Real-World Case Studies (Part 2 of 2)
by Lauro Rizzatti on 10-20-2025 at 6:00 am

The Rise, Fall, and Rebirth of In Circuit Emulation real world case studies figure 1

Recently, I had the opportunity to speak with Synopsys’ distinguished experts in speed adapters and in-circuit emulation (ICE). Many who know my professional background see me as an advocate for virtual, transactor-based emulation, hence I was genuinely surprised to discover the impressive results achieved by today’s speed… Read More


The Rise, Fall, and Rebirth of In-Circuit Emulation (Part 1 of 2)

The Rise, Fall, and Rebirth of In-Circuit Emulation (Part 1 of 2)
by Lauro Rizzatti on 09-11-2025 at 6:00 am

The Rise, Fall, and Rebirth of In Circuit Emulation Part 1 Figure 1

Introduction: The Historical Roots of Hardware-Assisted Verification

The relentless pace of semiconductor innovation continues to follow an unstoppable trend: the exponential growth of transistor density within a given silicon area. This abundance of available semiconductor fabric has fueled the creativity of design… Read More


Verific Design Automation at the 2025 Design Automation Conference

Verific Design Automation at the 2025 Design Automation Conference
by Lauro Rizzatti on 06-08-2025 at 8:00 am

62nd DAC SemiWiki

Rick Carlson, Verific Design Automation’s Vice President of Sales, is an EDA trends spotter. I was reminded of his prescience when he recently called to catch up and talk about Verific’s role as provider of front-end platforms powering an emerging EDA market.

Verific, he said, is joining forces with a group of well-funded startups… Read More


SNUG 2025: A Watershed Moment for EDA – Part 1

SNUG 2025: A Watershed Moment for EDA – Part 1
by Lauro Rizzatti on 04-15-2025 at 6:00 am

SNUG 2025 A Watershed Moment for EDA Figure 1

Hot on the heels of DVConUS 2025, the 35th annual Synopsys User Group (SNUG) Conference made its mark as a defining moment in the evolution of Synopsys—and the broader electronic design automation (EDA) industry. This year’s milestone event not only underscored Synopsys’ continued innovation but also affirmed the vision… Read More


The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)

The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)
by Lauro Rizzatti on 11-19-2024 at 10:00 am

Immensity of SW development Part 4 Table 1

The Impact of AI on Software and Hardware Development

Part 4 of this series analyzes how AI algorithmic processing is transforming software structures and significantly modifying processing hardware. It explores the marginalization of the traditional CPU architecture and demonstrates how software is increasingly dominatingRead More


The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)

The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)
by Lauro Rizzatti on 10-03-2024 at 10:00 am

Immensity of SW development Part 3 Figure 1

Part 3 of this 4-part series analyzes methods and tools involved in debugging software at different layers of the software stack.

Software debugging involves identifying and resolving issues ranging from functional misbehaviors to crashes. The essential requirement for validating software programs is the ability to monitor… Read More


The Immensity of Software Development the Challenges of Debugging (Part 1 of 4)

The Immensity of Software Development the Challenges of Debugging (Part 1 of 4)
by Lauro Rizzatti on 07-15-2024 at 10:00 am

Immensity of SW development Fig 1

Part 1 of this 4-part series introduces the complexities of developing and bringing up the entire software stack on a System on Chip (SoC) or Multi-die system. It explores various approaches to deployment, highlighting their specific objectives and the unique challenges they address.

Introduction

As the saying goes, it’s… Read More


Reduce Risk, Ensure Compliance: Hardware-Assisted Verification for Design Certification

Reduce Risk, Ensure Compliance: Hardware-Assisted Verification for Design Certification
by Lauro Rizzatti on 06-12-2024 at 10:00 am

Reduce risk ensure compliance Figure 1
Prologue

Peter was running late for two reasons. First, he encountered unexpected heavy traffic and arrived ten minutes late for a crucial meeting with a customer to run a compliance test of his new 6G phone design prototyped on FPGAs. This prototype’s success was pivotal, as it could secure a significant purchase order.Read More