Webinar: Enabling SoC Security and Reliability for HPC, AI & IoT with NVM OTP IP in TSMC N5

Webinar: Enabling SoC Security and Reliability for HPC, AI & IoT with NVM OTP IP in TSMC N5
by Admin on 03-26-2024 at 2:23 pm

Hardware security is essential for high-performance computing (HPC), AI, and Edge IoT applications when designing SoCs in advanced process nodes. These designs include Gigabits of SRAM and require storing >16Kb of repair information to meet yield requirements. Designers are facing the challenges of creating secure,

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GSA 2024 European Executive Forum

GSA 2024 European Executive Forum
by Admin on 03-15-2024 at 2:06 pm

The GSA European Executive Forum is our flagship event in Europe which, over two days, always attracts the very top speakers and attendees: 300 senior decision makers, the majority VP and C-level profiles.

Over the past 20 years, it has become the reference executive event for the semiconductor industry in the EMEA region.

This… Read More


Agile Analog Technology Showcase Event

Agile Analog Technology Showcase Event
by Admin on 02-26-2024 at 8:09 pm

Learn how innovative analog IP can help analog design engineers.

Agile Analog is transforming the analog IP industry, with Composa, our configurable, multi-process technology that automatically generates analog IP. We offer a wide-variety of novel analog IP solutions for Data Conversion, Power Management, IC Monitoring,… Read More


Webinar: Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs

Webinar: Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
by Admin on 01-08-2024 at 2:00 pm

Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly

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Webinar: Addressing UCIe 1.1 IP and System Level Verification Challenges

Webinar: Addressing UCIe 1.1 IP and System Level Verification Challenges
by Admin on 01-08-2024 at 1:39 pm

Thursday, February 8, 2024 | 9-10 a.m. PT

The Universal Chiplet Interconnect Express (UCIe) v1.0 standard was introduced in March of 2022 and v1.1 was published in July 2023. There is a huge demand for an open chiplet ecosystem that will unleash innovation across the compute continuum which in turn increases the demand for power

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Webinar: The Perfect Duo: Chiplet Design Meets Modern Data & IP Management

Webinar: The Perfect Duo: Chiplet Design Meets Modern Data & IP Management
by Admin on 01-05-2024 at 4:33 pm

In a world where the chiplet market is projected to soar to $50.5 billion in revenue by 2024, staying ahead of the game is crucial. This monumental shift in the IC design ecosystem necessitates a forward-thinking approach to navigate the sea of data and intricate Intellectual Properties (IPs) securely.

That’s why Keysight… Read More


Webinar: Auto-generation of Verification Infrastructure for IP to SoC

Webinar: Auto-generation of Verification Infrastructure for IP to SoC
by Admin on 11-15-2023 at 3:44 pm

DVClub Europe Meeting –November 2023

Agenda (BST):

12.00 GMT – Welcome and Introduction

Mike Bartley,Tessolve

12.00 GMT – Saving Development Time by Automating Verification infra from specifications

Anupam Bakshi, Agnisys

12.30 GMT – Generation of Functional Coverage for RISC-V Processor Verification

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Webinar: Automated Constraints Promotion Methodology from IP to SoC Designs for Complex Designs

Webinar: Automated Constraints Promotion Methodology from IP to SoC Designs for Complex Designs
by Admin on 10-30-2023 at 2:49 pm

IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will cover how automated SDC constraints promotion from the IP to SoC level provides high-quality SDC using Synopsys Timing Constraints

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