The philosophy of relying on a single, unified IP stack to lower your total cost of ownership is not a new concept invented just for the AI era. Semiconductor engineering teams have been weighing the trade-offs of piecemeal versus integrated intellectual property sourcing for decades. In previous process generations, veering… Read More
By Defacto Staff
Today’s chips are no longer just processors, they are entire systems. A System-on-Chip (SoC) brings together CPU clusters, accelerators, memories, interconnects and dozens of peripherals, often coming from many different teams and vendors. With AI, high-performance computing and IoT driving demand for … Read More
Ceva is expanding the reach of its neural processing technology with a next-generation NeuPro portfolio designed to serve everything from always-on sensors to AI infrastructure. The announcement introduces four NPU families sharing a common architecture and unified software stack, giving semiconductor developers a consistent… Read More
Thursday, November 5, 2026
11:00am PST | 2:00pm EST | 20:00 CET
As SoCs evolve into multi-die systems, getting data across a die-to-die interface is only part of the challenge. Architects must also preserve traffic behavior, bandwidth efficiency and quality of service as communication moves across physical chip boundaries.
DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog, Verilog, VHDL, PSS, SystemC and e, as well
Tuesday, November 10, 2026
8:00am PST | 11:00am EST | 17:00 CET
Functional verification establishes that a chip performs its intended functions. Hardware security assurance, however, addresses a different set of questions: Can sensitive information reach unauthorized destinations? Can protected state be modified unexpectedly?
Eric Hong is Vice President of Engineering at Mixel, a Silvaco company, where he leads the development of analog and mixed-signal IP, including high-speed PHY and SerDes solutions. Prior to Mixel, he held engineering leadership and technical roles at Nvidia, eSilicon, Samsung Electro-Mechanics, and Intel, leading the development… Read More
Featured Speakers:
As SoC complexity climbs, traditional verification can’t keep pace — and system-level bugs surface late, when they’re hardest to fix. By pairing Hardware-Assisted… Read More
The explosive growth of AI and accelerated computing is placing unprecedented demands on system-on-chip (SoC) design. Modern AI workloads require extremely high bandwidth, ultra-low latency, and energy-efficient data movement across increasingly heterogeneous architectures. As SoCs scale to incorporate clusters of… Read More
IP-XACT, defined by IEEE 1685, is a standard that pulls together IP packaging, integration, and reuse. For anyone building modern SoCs (Systems on Chip), IP-XACT isn’t just another XML schema: it is a productivity multiplier and a risk-reduction tool that brings order to your electronic system design.
What is IP-XACT?
IP-XACT… Read More
