TSMC’s CoPoS, generally described as Chip-on-Panel-on-Substrate, and Intel’s EMIB, or Embedded Multi-die Interconnect Bridge, address the same strategic problem: integrating increasingly large, heterogeneous chiplet systems. However, they attack different physical constraints. CoPoS is an emerging panel-level … Read More
Tag: intel
The Yield Partnership: Intel and PDF Solutions Tackle Advanced Nodes
One of the most difficult things to do in life is ask for help. This is inherently a big problem in the semiconductor industry dating back to the IDM days where silos of secrecy were established. As a result Intel has struggled with yield since the 14nm FinFET process nodes.
On the outside PDF Solutions is a publicly traded semiconductor… Read More
Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools
As advanced packaging becomes a critical enabler for next-generation semiconductor products, Intel continues to drive innovation through its Embedded Multi-die Interconnect Bridge (EMIB) technology. EMIB has emerged as a foundational packaging solution for heterogeneous integration, allowing multiple chiplets and… Read More
Webinar: Intel: Pushing EMIB Forward Design Methodology Insights with Synopsys Tools – SemiWiki
Date: Jun 25, 2026 | 9:00 AM PST
In this webinar, Intel will present how EMIB (Embedded Multi‑die Interconnect Bridge) enables compact, cost-effective multi‑die design while sustaining the bandwidth and power efficiency required for AI and datacenter designs. Intel will share an EMIB reference methodology built on Synopsys
Re-Spins Get You Fired, Says Intel CEO Lip-Bu Tan
Intel CEO Lip-Bu Tan’s statement that “re-spins get you fired” reflects the enormous pressure facing semiconductor companies as chip complexity, manufacturing costs, and competitive demands continue to rise. In the semiconductor industry, a “re-spin” occurs when a chip design must be revised and manufactured again because… Read More
ASML High-NA EUV is Not Ready for High-Volume Production
Contrary to the popular press, ASML High-NA EUV is not ready for logic production yet—and it may never be, at least not in the form originally envisioned. If you remember how long it took conventional EUV to become production-worthy—arguably 5–10 years—this should not come as a surprise. More importantly, this is no longer just… Read More
Webinar: Intel: From Construction to Signoff: 3DIC Methodology for Disaggregated Designs
Featured Speaker:
- Victoria Kolesov, Principal Engineer, Intel
In this Synopsys webinar, Intel will present how its disaggregated designs across client and server platforms have driven the evolution of robust 3D multi-die design construction and signoff methodologies. Intel will share practical experience using Synopsys’
SemiWiki Acquires IPnest!
After more than 15 years of collaboration with Dr. Eric Esteve and IPnest, SemiWiki has acquired the famed IP reports with Eric Esteve staying on through 2026 to ease the transition. Not only will SemiWiki provide the industry standard Interface IP and Design IP reports, SemiWiki will be expanding the depth and breadth of the coverage.… Read More
Elon Musk Needs to Put His Fab Money Where his Mouth is!
To me this is going to be one of the bigger Chicken Little moments in the history of semiconductors. Mostly because we are now a click driven society and the media is plagued by so called influencers that live and die by clicks. In my 40+ years as a semiconductor professional I have witnessed many of these Chicken Little moments with … Read More
Is Intel About to Take Flight?
The Pan Am–Boeing playbook and what Musk’s Terafab order could mean for Intel Foundry
“We either build the Terafab or we don’t have the chips.” That’s Elon Musk, speaking to Reuters, stating a supply constraint as plainly as anyone has stated one. TSMC is sold out. Samsung is committed. The existing supply chain can’t expand fast… Read More
