A response to Daniel Nenni’s “What’s Wrong with Intel?” article, which invited alternative views.
At the risk of calling down the forecast universal opprobrium, I’m going to disagree with Dan’s take on the centrality of Intel.
I don’t agree that Intel is too big/important to fail or that the US can’t succeed in semiconductors without… Read More
One of the most popular topics on the SemiWiki forum is Intel, which I understand. Many of us grew up with Intel, some of us have worked there, and I can say that the vast majority of us want Intel to succeed. The latest Intel PR debacle is the abrupt departure of CEO Pat Gelsinger. To me this confirms the answer to the question, “What is … Read More
Dan is joined by Dr. Tahir Ghani, Intel senior fellow and director of process pathfinding in Intel’s Technology Research Group. Tahir has a 30-year career at Intel working on many innovations, including strained silicon, high-K metal gate devices, FinFETs, RibbonFETs, and backside power delivery (BSPD), among others. He has… Read More
My first job out of college was migrating a DRAM chip from one process node to a newer node, and it was a 100% manual process that required many months of effort. That need to migrate semiconductor IP to newer nodes is still with us today, and much automation has been applied to digital circuits, however migrating analog IP has proven… Read More
This one-day Executive Conference will feature presentations from PDF Solutions executives, industry thought leaders, solutions partners and customers on the state of art and best practices to design, deploy, scale, and manage trusted AI / ML … Read More
Independent software vendors (ISVs) are unleashing a new wave of business innovation as they run AI directly on Intel® Core™ Ultra processors. By shifting AI workloads from the cloud to the client, businesses can lower SaaS costs, protect user privacy and data security, and enable novel use cases when AI has access to the full set… Read More
Anyone who has read my articles about IEDM in the past know I consider it a premiere conference covering developments of leading-edge semiconductor process technology. The 2024 conference will take place in San Francisco from December 7th through 11th.
AI – Lots of artificial… Read More
A successful multi-die design begins at the architecture exploration level. However, the architecture challenges are exacerbated for multi-die designs as performance and power need to be optimized across multiple heterogeneous and homogeneous dies. Disaggregating IPs based on workload demands, selecting the… Read More
The Universal Chiplet Interconnect Express™ (UCIe™) 1.0 specification was announced in early 2022 and a UCIe 1.1 update was released on August 8, 2023. This open standard facilitates the heterogeneous integration of die-to-die link interconnects within the same package. This is a fancy way of saying the standard opens the door… Read More
Entering the exhibit area of DAC on the first floor I was immediately faced with the Keysight EDA booth, and it was even larger than either the Synopsys or Cadence booths. They had a complete schedule of partners presenting in their theatre that included: Microsoft Azure, Riscure, Fermi Labs, BAE Systems, Alphawave, Intel Foundry,… Read More
