There are three critical goals that designers of custom digital designs and memories look to achieve with high sigma verification:
(1) obtaining accurate results,
(2) achieving results with good run-time (efficiency), and
(3) gaining proper insight into how their circuit is behaving along with an understanding of failure … Read More
Whether you use a gate-first or gate-last High-k Metal Gate implementation, yield will be your #1 concern at 28nm, which makes variation analysis and verification a big challenge. One of the consulting projects I have been working on with the foundries and top fabless semiconductor companies is High-Sigma Monte Carlo (HSMC) … Read More
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ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era