There is an intriguingly amorphous term in FPGA design circles lately: Quality of Results, or QoR. Fitting a design in an FPGA is just the start – is a design optimal in real estate, throughput, power consumption, and IP reuse? Paradoxically, as FPGAs get bigger and take on bigger signal processing problems, QoR has become a larger… Read More
Tag: high-level synthesis
Calypto 2013 Report
Each year Calypto runs a survey of end-users. This year’s survey and report has two parts, power reduction and high level synthesis (HLS).
The topics covered are:
- survey methodology and demographics
- top methods used to reduce power
- engineering time spent on specfiic RTL tasks to reduce power
- plans to deploy RTL power reduction
Forte Rises
Over the past few months there has been a bit of back-and-forth concerning the 2012 market data indicating that Forte Designs Systems had taken over the top spot (by revenue) in the high-level synthesis (HLS) market (see stories hereand here). Having worked in this segment for Synfora as VP of Marketing, and as a consultant to AutoESL,… Read More
Mentor catapults Calypto
Mentor has transferred its Catapult (high level synthesis) product line, including the people, to Calypto. Terms were not disclosed but apparently it is a non-cash deal. Calypto gets the product line. Mentor gets a big chunk of ownership of Calypto. So maybe the right way to look at this is as a partial acquisition of Calypto.
It … Read More