Huawei’s and SMIC’s Requirement for 5nm Production: Improving Multipatterning Productivity

Huawei’s and SMIC’s Requirement for 5nm Production: Improving Multipatterning Productivity
by Fred Chen on 04-23-2024 at 10:00 am

Self aligned blocking scheme

There has been much interest in Huawei’s and SMIC’s plans for 5nm production in the near future. Since there is no use of EUV in China, immersion DUV lithography (with a 76 nm pitch resolution) is expected to be used along with pitch quartering to achieve pitches in the 20-30 nm range expected for the 5nm and 3nm nodes [1].… Read More


Horizontal, Vertical, and Slanted Line Shadowing Across Slit in Low-NA and High-NA EUV Lithography Systems

Horizontal, Vertical, and Slanted Line Shadowing Across Slit in Low-NA and High-NA EUV Lithography Systems
by Fred Chen on 01-11-2022 at 6:00 am

EUV shadowing across slit

EUV lithography systems continue to be the source of much hope for continuing the pace of increasing device density on wafers per Moore’s Law. Recently, although EUV systems were originally supposed to help the industry avoid much multipatterning, it has not turned out to be the case [1,2]. The main surprise has been the

Read More

Three Interesting Things from TSMC!

Three Interesting Things from TSMC!
by Daniel Nenni on 01-13-2017 at 12:00 pm

First, the TSMC Museum of Innovation is now open and it’s quite impressive. Located right below Fab 12, it is definitely worth an hour of your time. Second, Morris Chang was on the investor call which made it much more interesting, especially his comments on the recent Report to the President on U.S. semiconductor leadership. Third,… Read More