Patterns looking inside, not just between, logic cells

Patterns looking inside, not just between, logic cells
by Don Dingee on 12-27-2013 at 5:00 pm

Traditional logic testing relies on blasting pattern after pattern at the inputs, trying to exercise combinations to shake faults out of logic and hopefully have them manifested at an observable pin, be it a test point or a final output stage. It’s a remarkably inefficient process with a lot of randomness and luck involved.

Getting… Read More


IC Test Sessions at SEMICON West 2012

IC Test Sessions at SEMICON West 2012
by Beth Martin on 07-02-2012 at 1:43 pm

SEMICON West is coming up this July 10-12 at the Moscone Center in San Francisco. It covers a broad swath of the microelectronics supply chain, but I was particularly interested in the test sessions. Here are two that I recommend.

The Value of Test for Semiconductor Yield Learning” on Tuesday, July 10, at 1:30p. The… Read More