CEO Interview: Mark Williams of Pulsic

CEO Interview: Mark Williams of Pulsic
by Daniel Nenni on 02-19-2021 at 6:00 am

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Pulsic recently announced its new “freemium” product Animate Preview and we had the chance to chat with Mark Williams, President and CEO of Pulsic.  Mark explained details of  the product and the new business model that could change the direction of the traditional EDA business model structure.

What brought you to the semiconductorRead More


CEO Interview: Simon Butler of Methodics

CEO Interview: Simon Butler of Methodics
by Daniel Nenni on 10-24-2016 at 7:00 am

It has been interesting to watch Methodics transform from an EDA company with their VersIC design management product to Life Cycle Management with ProjectIC, and now a Systems Company with WarpStor. Methodics was founded in 2006 by 2 ex-Cadence experts in the Custom IC design tools space, Simon Butler and Fergus Slorach. Today… Read More


Teach Yourself Silvaco

Teach Yourself Silvaco
by Paul McLellan on 05-12-2014 at 10:53 am

In the dim and distant past, if you wanted to learn how to use a particular EDA tool then you would go on a training course. This would often be multiple days and often a significant dollar investment too. For most EDA companies, that option still exists and the big 3 have quite extensive training catalogs.

But nowadays it is often easier… Read More


Virtuoso Has Twins

Virtuoso Has Twins
by Paul McLellan on 10-18-2012 at 6:01 pm

Cadence has apparently announced that going forward the Virtuoso environment is going to be split into two and offered as two separate code-streams, the current IC6.x and a new IC12.x. The idea is to introduce a new product with features that were specifically developed for new technologies such as double patterning aware layout… Read More


Analog Constraint Standards

Analog Constraint Standards
by Paul McLellan on 09-20-2011 at 8:00 am

Over the years there has been a lot of standard creation in the IC design world to allow interoperability of tools from different vendors. One area of recent interest is interoperable constraints for custom IC design. Increasingly, analog design layout is becoming more automated. Advanced process nodes require trial layouts… Read More