AI System Connectivity for UCIe and Chiplet Interfaces Demand Escalating Bandwidth Needs

AI System Connectivity for UCIe and Chiplet Interfaces Demand Escalating Bandwidth Needs
by Kalar Rajendiran on 05-27-2024 at 10:00 am

Alphwave Semi UCIe PHY Support for All Package Types

Artificial Intelligence (AI) continues to revolutionize industries, from healthcare and finance to automotive and manufacturing. AI applications, such as machine learning, deep learning, and neural networks, rely on vast amounts of data for training, inference, and decision-making processes. As AI algorithms become … Read More


Pairing RISC-V cores with NoCs ties SoC protocols together

Pairing RISC-V cores with NoCs ties SoC protocols together
by Don Dingee on 10-05-2023 at 6:00 am

An architecture pairing RISC-V cores with NoCs

Designers have many paths for differentiating RISC-V solutions. One path launches into various RISC-V core customizations and extensions per the specification. Another focuses on selecting and assembling IP blocks in a complete system-on-chip (SoC) design around one or more RISC-V cores. A third is emerging: interconnecting… Read More


Analog Design Acceleration for Chiplet Interface IP

Analog Design Acceleration for Chiplet Interface IP
by Tom Simon on 03-24-2022 at 10:00 am

Analog Generators Boost Designer Productivity

Compared to the automation of digital design, the development of automation for analog has taken a much more arduous path. Over the decades there have been many projects both academic and commercial to accelerate and improve the process for analog design. One of the most interesting efforts in this area is being spearheaded by … Read More