Bug localization continues to be a challenge for both bug triage and root-cause analysis. Agentic approaches suggest a way forward. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas.… Read More
In a bold move that underscores the accelerating convergence of electronic design automation (EDA) and mechanical engineering, Cadence Design Systems announced its agreement to acquire Hexagon AB’s Design & Engineering (D&E) business for approximately €2.7 billion, equivalent to about $3.16 billion. This… Read More
2025 Keynote Addresses from Industry Leaders:
Alphawave Semi, Arm, Cadence Design Systems, Keysight, Open Compute Project, Synopsys, Teradyne
2025’s Main Topics Included:
AI/ML Acceleration, Open Chiplet Economy, Advanced Packaging Methods, Die-to-die Interfaces, Working … Read More
Designing semiconductor chips has traditionally been costly and controlled by a few major Electronic Design Automation (EDA) vendors—Cadence, Synopsys, and Siemens EDA who dominate with proprietary tools protected by NDAs and restrictive licenses. Fabrication also requires expensive, often export-controlled equipment.… Read More
What does the future hold for marine CFD simulation? Join us at the CadenceCONNECT: CFD Innovations for Marine Applications seminar to find out!
Historic software uses methods for solving that simply do not have the scalability to meet the needs of marine evolution. Cadence CFD analysis gives you an automatic and efficient computation
Join industry leaders and Cadence cloud experts at this free must-attend Cloud event of the year to explore the latest cloud EDA innovations, share ideas, and grow your professional connections.
All attendees will receive a giveaway and a chance to win raffle prizes.
DATE: September 25, 2025
TIME: 10:00am – 1:45pm… Read More
Speaker: Kee Tat Ong, Principal Application Engineer
10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure
11:00am~11:15am Q&A
Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order… Read More
Speaker: Hong-Cheang Quek, AE Director
10:00am~11:00am iPegasus Verification System for Virtuoso Studio
11:00am~11:15am Q&A
Description: Today’s complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle… Read More
Speaker: Soo Chuan Tang, Principal Application Engineer
10:00am~11:00am Next-Generation Spectre FX FastSPICE Simulator and Spectre X Integration with GPU
11:00am~11:15am Q&A
Description: Leveraging a FastSPICE engine built from the ground up, Cadence Spectre FX Simulator delivers performance and accuracy improvements… Read More
