Intel Foundry Delivers!

Intel Foundry Delivers!
by Daniel Nenni on 05-05-2025 at 10:00 am

Intel Foundry Direct Connect Hall 4 1024x576

Now that the dust has settled, I will give you my take on the Intel Foundry event. Some might call me a semiconductor event critic as I have attended hundreds of them over the last 40 years starting with the Design Automation Conference in 1984. Foundry events are my favorite because they really are the pulse of the semiconductor industry,… Read More


Designing and Simulating Next Generation Data Centers and AI Factories

Designing and Simulating Next Generation Data Centers and AI Factories
by Kalar Rajendiran on 04-22-2025 at 10:00 am

Digital Twin and the AI Factory Lifecycle

At NVIDIA’s recent GTC conference, a Cadence-NVIDIA joint session provided insights into how AI-powered innovation is reshaping the future of data center infrastructure. Led by Kourosh Nemati, Senior Data Center Cooling and Infrastructure Engineer from NVIDIA and Sherman Ikemoto, Sales Development Group Director from … Read More


How Cadence is Building the Physical Infrastructure of the AI Era

How Cadence is Building the Physical Infrastructure of the AI Era
by Kalar Rajendiran on 04-21-2025 at 6:00 am

Phases of AI Adoption

At the 2025 NVIDIA GTC Conference, CEO Jensen Huang delivered a sweeping keynote that painted the future of computing in bold strokes: a world powered by AI factories, built on accelerated computing, and driven by agentic, embodied AI capable of interacting with the physical world. He introduced the concept of Physical AI—intelligence… Read More


Design IP Market Increased by All-time-high: 20% in 2024!

Design IP Market Increased by All-time-high: 20% in 2024!
by Eric Esteve on 04-14-2025 at 10:00 am

Top5 License

Design IP revenues achieved $8.5B in 2024 and this is an all-time-high growth of 20%. Wired Interface is still driving Design IP growth with 23.5% but we see the Processor category also growing by 22.4% in 2024. This is consistent with the Top 4 IP companies made of ARM (mostly focused on processor) and a team leading wired interface… Read More


Webinar: How Embedded Data Management in ​​​​​​​Cadence Virtuoso Studio Supercharges Analog Design (Europe)

Webinar: How Embedded Data Management in ​​​​​​​Cadence Virtuoso Studio Supercharges Analog Design (Europe)
by Admin on 03-24-2025 at 7:38 am

Join us on April 9 to discover how to unlock the power of built-in data management using Keysight Design Data Management (SOS) within Cadence Virtuoso Studio.

Here’s What You Can Learn

  • How to eliminate design rework and data loss issue
  • How this fully embedded solution enhances productivity and ensures faster Time-to-Market
  • Live
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Webinar: How Embedded Data Management in ​​​​​​​Cadence Virtuoso Studio Supercharges Analog Design (USA)

Webinar: How Embedded Data Management in ​​​​​​​Cadence Virtuoso Studio Supercharges Analog Design (USA)
by Admin on 03-24-2025 at 7:35 am

How Embedded Data Management in Cadence Virtuoso Studio Supercharges Analog Design

Join us on April 8 to discover how to unlock the power of built-in data management using Keysight Design Data Management (SOS) within Cadence Virtuoso Studio.

Here’s What You Can Learn

  • How to eliminate design rework and data loss issue
  • How this
Read More

Embracing the Chiplet Journey: The Shift to Chiplet-Based Architectures

Embracing the Chiplet Journey: The Shift to Chiplet-Based Architectures
by Kalar Rajendiran on 02-12-2025 at 6:00 am

Chiplets A New Abstraction Layer

The semiconductor industry is facing a paradigm shift. Traditional scaling, once driven by Moore’s Law, is slowing down. For years, moving to smaller process nodes led to lower transistor costs and better performance. However, scaling from node to node now offers fewer benefits as wafer costs rise much more than the historical… Read More


Webinar: Enabling RF and mmWave Design Success with Advanced Models

Webinar: Enabling RF and mmWave Design Success with Advanced Models
by Admin on 01-24-2025 at 2:22 pm

Time: 06:00 ET / 11:00 GMT / 12:00 CET / 15:00 GST

Traditionally, measured S-parameter data files in the RF and mmWave industry have been the most commonly available “model” to represent passive devices as well as active devices in some cases. However, S-parameters are not accurate enough when designing active devices in which

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CadenceTECHTALK: Addressing Thermal Design Challenges with In-Design Analysis

CadenceTECHTALK: Addressing Thermal Design Challenges with In-Design Analysis
by Admin on 01-24-2025 at 1:55 pm

A “PCB thermal analysis” design activity has traditionally involved the PCB designer transferring a finished design to a dedicated thermal analysis tool. While this has indeed successfully contributed to numerous PCB thermal signoffs in the past, there are inefficiencies that can be mitigated with the use of Cadence’s Allegro… Read More


Webinar: Getting Started with Electrical Constraints in OrCAD X

Webinar: Getting Started with Electrical Constraints in OrCAD X
by Admin on 01-24-2025 at 1:53 pm

Properly constraining your design is a must whether designing for high-speed, high-voltage, or high-density. Electrical Constraints in OrCAD X give designers the tools to control routing based on impedance and timing requirements, allowing users to analyze and tune those signals and reuse information between designs.

Join… Read More