In a bold move that underscores the accelerating convergence of electronic design automation (EDA) and mechanical engineering, Cadence Design Systems announced its agreement to acquire Hexagon AB’s Design & Engineering (D&E) business for approximately €2.7 billion, equivalent to about $3.16 billion. This… Read More
Tag: cadence
Chiplet Summit 2026
All the Solutions for Developing Chiplets
2025 Keynote Addresses from Industry Leaders:
Alphawave Semi, Arm, Cadence Design Systems, Keysight, Open Compute Project, Synopsys, Teradyne
2025’s Main Topics Included:
AI/ML Acceleration, Open Chiplet Economy, Advanced Packaging Methods, Die-to-die Interfaces, Working … Read More
Free and Open Chip Design Tools: Opportunities, Challenges, and Outlook
Designing semiconductor chips has traditionally been costly and controlled by a few major Electronic Design Automation (EDA) vendors—Cadence, Synopsys, and Siemens EDA who dominate with proprietary tools protected by NDAs and restrictive licenses. Fabrication also requires expensive, often export-controlled equipment.… Read More
CadenceCONNECT: CFD Innovations for the Marine Industry
What does the future hold for marine CFD simulation? Join us at the CadenceCONNECT: CFD Innovations for Marine Applications seminar to find out!
Historic software uses methods for solving that simply do not have the scalability to meet the needs of marine evolution. Cadence CFD analysis gives you an automatic and efficient computation
Cloud Tech Day 2025
Join industry leaders and Cadence cloud experts at this free must-attend Cloud event of the year to explore the latest cloud EDA innovations, share ideas, and grow your professional connections.
All attendees will receive a giveaway and a chance to win raffle prizes.
DATE: September 25, 2025
TIME: 10:00am – 1:45pm… Read More
Reimagining Custom Design with AI-Powered Virtuoso Studio
Join us for an in-person seminar to explore the future of custom design and migration with AI-powered Virtuoso Studio. Discover how the latest innovations from Cadence are transforming analog, custom, RFIC, and MMIC design. Learn how these advancements enable faster, smarter insight analysis and more precise workflows using
CadenceTECHTALK: Reduce SMT Parasitic Design Failures with Innovative Filter Topologies
This webinar explores strategies for optimizing SMT filter designs, addressing spurious responses, parasitic behaviors, and PCB layout challenges using Cadence’s Microwave Office and Modelithics simulation models to ensure accurate and reliable performance.
Webinar Details
Join our webinar to discover challenges and
CadenceTECHTALK: PSpice-Based Reliability Analysis for Critical Systems
DATE: Wednesday, September 10, 2025
TIME: 8:00am PDT | 11:00am EDT | 3:00pm GMT | 8:30pm IST
In mission-critical sectors like aerospace, defense, and space systems, reliability is everything. Failures carry enormous risk, making rigorous design validation essential. This webinar explores how advanced PSpice simulation … Read More
CadenceTECHTALK: Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure
Speaker: Kee Tat Ong, Principal Application Engineer
10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure
11:00am~11:15am Q&A
Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order… Read More
CadenceTECHTALK: iPegasus Verification System for Virtuoso Studio
Speaker: Hong-Cheang Quek, AE Director
10:00am~11:00am iPegasus Verification System for Virtuoso Studio
11:00am~11:15am Q&A
Description: Today’s complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle… Read More