Probably one of the most anticipated semiconductor investor calls was held last week and it did not disappoint. It was Lip-Bu Tan’s first full quarter since he took over as CEO. In the resulting discussions on the SemiWiki Forum I am viewed as overly optimistic of Intel’s recent pivot. That is true, I am optimistic, but my observations… Read More
CadenceCONNECT: Jasper User Group 2025 is October 29 and 30 in San Jose, CA. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies… Read More
Are you driving design change? Do you think you have successfully overcome challenges that may affect the electronic revolution? CadenceLIVE is willing to provide a platform to share your story. Come here to show your expertise, share and provide professional skills to help engineers solve the complexity and challenges they… Read More
IR signoff for advanced SoCs and 3D-ICs is a major challenge due to extremely large and complex power networks that can exceed 100 billion nodes. Designers are faced with very long runtimes and very large compute resource requirements amounting to thousands of CPUs and 100TB+ memory to run a full-chip flat.
In this
DATE: Wednesday, June 18, 2025
TIME: 8:00am PDT | 11:00am EDT | 3:00pm GMT | 8:30pm IST
Experience the future of Engineering BOM Management with OrCAD X. Our innovative Live BOM feature revolutionizes your design and supply chain processes, empowering your projects with unmatched visibility, optimization, and control.
Join… Read More
The increasing complexity of chip designs that leverage 3D-IC technology, heterogeneous integration, and other manufacturing advancements, emphasizes the need for accurate modeling of electromagnetic (EM) crosstalk. EM solvers continue to play a key role in solving larger problems both in terms of layout
Cadence, a DAC 2025 industry sponsor, will exhibit in booth 1609 at the 62nd Design Automation Conference at San Francisco’s Moscone West Convention Center.
Highlights:
Paul Cunningham, SVP and GM of the System Verification Group, Cadence, will speak at Cooley’s DAC Troublemaker Panel. This discussion will be an open… Read More
Explore how cutting-edge tools from Cadence are transforming RF PCB design for wireless, aerospace, and automotive innovations. This webinar showcases the seamless integration of Allegro X and the AWR Design Environment to simplify RF IP integration and streamline full PCB system design. Learn how automation and advanced… Read More
Now that the dust has settled, I will give you my take on the Intel Foundry event. Some might call me a semiconductor event critic as I have attended hundreds of them over the last 40 years starting with the Design Automation Conference in 1984. Foundry events are my favorite because they really are the pulse of the semiconductor industry,… Read More
At NVIDIA’s recent GTC conference, a Cadence-NVIDIA joint session provided insights into how AI-powered innovation is reshaping the future of data center infrastructure. Led by Kourosh Nemati, Senior Data Center Cooling and Infrastructure Engineer from NVIDIA and Sherman Ikemoto, Sales Development Group Director from … Read More
