Cadence’s Strategic Leap: Acquiring Hexagon’s Design & Engineering Business

Cadence’s Strategic Leap: Acquiring Hexagon’s Design & Engineering Business
by Admin on 09-05-2025 at 8:00 am

Cadence Hexagon

In a bold move that underscores the accelerating convergence of electronic design automation (EDA) and mechanical engineering, Cadence Design Systems announced its agreement to acquire Hexagon AB’s Design & Engineering (D&E) business for approximately €2.7 billion, equivalent to about $3.16 billion. This… Read More


Free and Open Chip Design Tools: Opportunities, Challenges, and Outlook

Free and Open Chip Design Tools: Opportunities, Challenges, and Outlook
by Admin on 08-24-2025 at 10:00 am

OPen EDA Ecosystem 2025 SemiWiki

Designing semiconductor chips has traditionally been costly and controlled by a few major Electronic Design Automation (EDA) vendors—Cadence, Synopsys, and Siemens EDA who dominate with proprietary tools protected by NDAs and restrictive licenses. Fabrication also requires expensive, often export-controlled equipment.… Read More


CadenceCONNECT: CFD Innovations for the Marine Industry

CadenceCONNECT: CFD Innovations for the Marine Industry
by Admin on 08-21-2025 at 2:37 am

What does the future hold for marine CFD simulation? Join us at the CadenceCONNECT: CFD Innovations for Marine Applications seminar to find out!

Historic software uses methods for solving that simply do not have the scalability to meet the needs of marine evolution. Cadence CFD analysis gives you an automatic and efficient computation

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Reimagining Custom Design with AI-Powered Virtuoso Studio

Reimagining Custom Design with AI-Powered Virtuoso Studio
by Admin on 08-21-2025 at 2:22 am

Join us for an in-person seminar to explore the future of custom design and migration with AI-powered Virtuoso Studio. Discover how the latest innovations from Cadence are transforming analog, custom, RFIC, and MMIC design. Learn how these advancements enable faster, smarter insight analysis and more precise workflows using

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CadenceTECHTALK: Reduce SMT Parasitic Design Failures with Innovative Filter Topologies

CadenceTECHTALK: Reduce SMT Parasitic Design Failures with Innovative Filter Topologies
by Admin on 08-21-2025 at 2:12 am

This webinar explores strategies for optimizing SMT filter designs, addressing spurious responses, parasitic behaviors, and PCB layout challenges using Cadence’s Microwave Office and Modelithics simulation models to ensure accurate and reliable performance.

Webinar Details

Join our webinar to discover challenges and

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CadenceTECHTALK: PSpice-Based Reliability Analysis for Critical Systems

CadenceTECHTALK: PSpice-Based Reliability Analysis for Critical Systems
by Admin on 08-21-2025 at 2:10 am

DATE: Wednesday, September 10, 2025

TIME: 8:00am PDT | 11:00am EDT | 3:00pm GMT | 8:30pm IST

In mission-critical sectors like aerospace, defense, and space systems, reliability is everything. Failures carry enormous risk, making rigorous design validation essential. This webinar explores how advanced PSpice simulation … Read More


CadenceTECHTALK: Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure

CadenceTECHTALK: Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure
by Admin on 08-21-2025 at 2:08 am

Speaker: Kee Tat Ong, Principal Application Engineer

10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure

11:00am~11:15am Q&A

Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order… Read More


CadenceTECHTALK: iPegasus Verification System for Virtuoso Studio

CadenceTECHTALK: iPegasus Verification System for Virtuoso Studio
by Admin on 08-21-2025 at 2:06 am

Speaker: Hong-Cheang Quek, AE Director

10:00am~11:00am iPegasus Verification System for Virtuoso Studio

11:00am~11:15am Q&A

Description: Today’s complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle… Read More