This webinar provides engineers with a science-driven framework for power supply design, rooted in the physics of electromagnetic energy flow. Inspired by Ralph Morrison’s pioneering approach, the session begins with core principles of energy behavior, then explores how current, fields, and waves interact inside
Tag: cadence
CadenceLIVE Silicon Valley 2026
Join us on April 16 for CadenceLIVE Silicon Valley 2026, where Cadence technology users connect with the engineers and industry leaders who develop the solutions and the industry experts who influence market trends.
Participants experience a day of learning, connection, and cutting-edge technology shaping the future of electronic… Read More
Agentic Bug Localization. Innovation in Verification
Bug localization continues to be a challenge for both bug triage and root-cause analysis. Agentic approaches suggest a way forward. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas.… Read More
Cadence’s Strategic Leap: Acquiring Hexagon’s Design & Engineering Business
In a bold move that underscores the accelerating convergence of electronic design automation (EDA) and mechanical engineering, Cadence Design Systems announced its agreement to acquire Hexagon AB’s Design & Engineering (D&E) business for approximately €2.7 billion, equivalent to about $3.16 billion. This… Read More
Chiplet Summit 2026
All the Solutions for Developing Chiplets
2025 Keynote Addresses from Industry Leaders:
Alphawave Semi, Arm, Cadence Design Systems, Keysight, Open Compute Project, Synopsys, Teradyne
2025’s Main Topics Included:
AI/ML Acceleration, Open Chiplet Economy, Advanced Packaging Methods, Die-to-die Interfaces, Working … Read More
Free and Open Chip Design Tools: Opportunities, Challenges, and Outlook
Designing semiconductor chips has traditionally been costly and controlled by a few major Electronic Design Automation (EDA) vendors—Cadence, Synopsys, and Siemens EDA who dominate with proprietary tools protected by NDAs and restrictive licenses. Fabrication also requires expensive, often export-controlled equipment.… Read More
CadenceTECHTALK: Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure
CadenceTECHTALK: Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure
Speaker: Kee Tat Ong, Principal Application Engineer
10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure
11:00am~11:15am Q&A
Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order… Read More
CadenceTECHTALK: iPegasus Verification System for Virtuoso Studio
Speaker: Hong-Cheang Quek, AE Director
10:00am~11:00am iPegasus Verification System for Virtuoso Studio
11:00am~11:15am Q&A
Description: Today’s complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle… Read More
CadenceCONNECT: Photonics and Quantum Technologies
Event Summary
The year 2025 is both a turning point for integrated photonics as a key enabler for AI, physical and infrastructure interconnect, and the International Year of Quantum (IYQ). In our event, we are going to explore the enabling technologies shared by these two exciting fields. While these systems need to exist in a broader
Why I Think Intel 3.0 Will Succeed
Probably one of the most anticipated semiconductor investor calls was held last week and it did not disappoint. It was Lip-Bu Tan’s first full quarter since he took over as CEO. In the resulting discussions on the SemiWiki Forum I am viewed as overly optimistic of Intel’s recent pivot. That is true, I am optimistic, but my observations… Read More