Join us on April 9 to discover how to unlock the power of built-in data management using Keysight Design Data Management (SOS) within Cadence Virtuoso Studio.
Here’s What You Can Learn
- How to eliminate design rework and data loss issue
- How this fully embedded solution enhances productivity and ensures faster Time-to-Market
- Live
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How Embedded Data Management in Cadence Virtuoso Studio Supercharges Analog Design
Join us on April 8 to discover how to unlock the power of built-in data management using Keysight Design Data Management (SOS) within Cadence Virtuoso Studio.
Here’s What You Can Learn
- How to eliminate design rework and data loss issue
- How this
…
Read More
The semiconductor industry is facing a paradigm shift. Traditional scaling, once driven by Moore’s Law, is slowing down. For years, moving to smaller process nodes led to lower transistor costs and better performance. However, scaling from node to node now offers fewer benefits as wafer costs rise much more than the historical… Read More
A “PCB thermal analysis” design activity has traditionally involved the PCB designer transferring a finished design to a dedicated thermal analysis tool. While this has indeed successfully contributed to numerous PCB thermal signoffs in the past, there are inefficiencies that can be mitigated with the use of Cadence’s Allegro… Read More
Properly constraining your design is a must whether designing for high-speed, high-voltage, or high-density. Electrical Constraints in OrCAD X give designers the tools to control routing based on impedance and timing requirements, allowing users to analyze and tune those signals and reuse information between designs.
Join… Read More
About this event
Thank you to our sponsors, Synopsys and Cadence
The Trends in System Design event, hosted by DESN in Reading on February 6th, will be open to both members and non-members. We will examine emerging trends in semiconductor system design, with a particular focus on how AI/ML is being used in product design and the design… Read More
Historically, PCB power distribution networks (PDNs) have been designed based on rules of thumb, such as “put a 0.1uF decoupling cap down for every power pin on the device”. These can lead to more capacitors than necessary, taking up additional space in the layout and driving up cost of the final assembly. In addition, they can lead… Read More
