Analyzing Memory Bus to Meet with DDR Specifications

Analyzing Memory Bus to Meet with DDR Specifications
by Admin on 04-14-2022 at 10:00 am

Part of Simulating for High-Speed Digital Insights series

April 14, 2022 | 10:00 AM PT / 1:00 PM ET

Due to ever increasing data demand, the speed grade for memory is now in the multi-gigabit range. Memory bus design becomes a lot more complicated with tighter design margins due to higher crosstalk between vias and traces along with… Read More


Enterprise SSD SOC’s Call for a Different Interconnect Approach

Enterprise SSD SOC’s Call for a Different Interconnect Approach
by Tom Simon on 03-01-2016 at 12:00 pm

The move to SSD storage for enterprise use brings with it the need for difficult to design enterprise capable SSD controller SOC’s. The benefits of SSD in hyperscale data centers are clear. SSD’s offer higher reliability due to the elimination of moving parts. They have a smaller foot print, use less power and offer much better performance.… Read More


Xilinx picks another winner…

Xilinx picks another winner…
by Luke Miller on 07-31-2013 at 7:00 pm

Just as important as block RAMs, IO and DSP48’s is what interconnect or fabric is going to be used when considering SoC FPGA designs. I think Xilinx has found the winning combination. What is paramount to the new SoC FPGA methodologies is not only the challenge of moving huge amounts of data around; we are now to consider data… Read More


Driving in the bus lane

Driving in the bus lane
by Paul McLellan on 12-08-2011 at 1:16 pm

Modern microprocessor and memory designs often have hundreds of datapaths that traverse the width of the chip, many of them very wide (over one thousand signals). To meet signal timing and slope targets for these buses, designers must insert repeater cells to improve the speed of the signal. Until now, the operations associated… Read More