I met Moshik Rubin (Sr. Group Director, Product Marketing and BizDev in the System Verification Group at Cadence) at DVCon to talk about PSS (the Portable Stimulus Standard) and Perspec, Cadence’s platform to support PSS. This was the big picture view I was hoping for, following more down in the details views from earlier talks.… Read More
Innovation in analog design moves slowly, not from lack of desire for better methods from designers or lack of effort and ideas from design tech innovators, but simply because the space is so challenging. Continuous time and signals, and variances in ambient/process characteristics represent a multi-dimensional space across… Read More
We have talked about metamorphic testing before. Here is a clever application to testing an AMS subsystem. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.… Read More
Automotive electronics is a fast-moving space, especially around sensing and distilling intelligence from that sensing. This serves three main pillars: autonomy, electrification and advances in the car cockpit. Autonomy at multiple levels remains an important goal and continues to advance, technically and geographically.… Read More
While Cadence and Synopsys were sharing a lot of detail over the past few years about what they were doing in AI, Siemens EDA seemed content to offer a very general picture about their intentions without getting into a lot of detail. At DVCon 2025 they finally pulled back the curtain. Why wait until now to announce?
Darron May (Director… Read More
As usual I check in on Accellera activities each year at DVCon. Lu Dai (chair) gave an opening talk at the Accellera lunch, with contributions from other speakers on a few topics. In the afternoon I heard an update on PSS 3.0. What follows is a quick summary with my own musings on behavioral coverage.
Karsten … Read More
I mentioned in an earlier blog that multiple presentations at DVCon 2025 went all-in on AI-assisted design and verification. The presentation was one such example, looking very much at top-down AI-expert application of agentic flows to design and verification. AlphaDesign is a new startup out of UC Santa Barbara headed by William… Read More
DVCon 2025 was unquestionably a forum for pulling out all the stops in AI-based (RTL) design and verification, particularly around generative AI and agentic methods. I heard three product pitches and a keynote and have been told that every AI talk was standing room only. A pitch from Rise-DA particularly appealed to me because … Read More
What’s new in debugging multi-/many-core systems? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.
This month’s pick is Post-Silicon… Read More
Modern semiconductor devices, a far cry from the chips we once knew, are now highly complex intelligent systems used in datacenters, communications infrastructure, in consumer electronics, automotive, home and office automation, almost everywhere. All such applications build around large subsystems, invariably compute,… Read More
