eSilicon Demonstrates Potent Memory IP Evaluation Platform

eSilicon Demonstrates Potent Memory IP Evaluation Platform
by Tom Simon on 11-18-2016 at 4:00 pm

With memories taking up in some cases over 50% of the area of many ASIC designs, their selection and implementation can affect everything from power and timing to the choice of packaging. As a result, the process of deciding among all the options for ASIC memories becomes time and energy intensive. Memory selection even affects … Read More