Sarcina Democratizes 2.5D Package Design with Bump Pitch Transformers

2.5D package design is rapidly finding its stride in a wide variety of applications, including AI. While there are still many challenges to its widespread adoption, the chiplet approach is becoming more popular compared to monolithic design. However, the required market to create a chiplet ecosystem is still under development. As package design complexity continues to rise, system partitioning, verification, and power management remain critical and challenging to fulfill. Additionally, package design presents secondary problems, including thermal and mechanical stress constraints, which, combined with the sheer cost of the package, make the design of advanced packages very challenging.

Advanced packaging is the domain of Sarcina Technology. Recent announcements from the company have illustrated how these challenges can be overcome. Let’s see how Sarcina democratizes 2.5D package design with something called Bump Pitch Transformers.

What is a Bump Pitch Transformer?

If you are a sci-fi movie buff, the term “transformer” might bring to mind something interesting, but it’s not relevant to the innovation discussed here for 2.5D package design. What Sarcina is addressing is the cost and complexity of the package for 2.5D designs.

Current advanced 2.5D packaging uses a substrate to transpose a chip’s microbump pitch from 40-50 micrometers to the package’s 130 micrometer bump pitch. This is typically done with a silicon TSV (through-silicon via) interposer. While this approach is effective, these substrates are very expensive, in short supply, and complex to design, resulting in lead-time and cost challenges for many advanced designs.

Sarcina’s Bump Pitch Transformer (BPT) approach uses silicon bridge technology, replacing silicon TSV interposers with more cost-effective re-distribution layers (RDL). This architecture is ideal for homogeneous and heterogeneous chiplet integration, targeting high-performance computing (HPC) devices for AI, data center, microprocessor, and networking applications.

By delivering lower costs and faster design times, Sarcina aims to democratize 2.5D package design, making it more readily available to companies to solve a wider range of problems.

Details and Applications

Sarcina’s BPT is effectively a wafer fan-out RDL technology which, thanks to its maturity, delivers lower costs and shorter lead times. This will help system designers optimize AI for new, lower-cost applications, effectively expanding the market. The company is currently engaging customers with two Bump Pitch Transformer options.

The first option (Option 1 above) creates a silicon bridge in high-density applications to connect the I/Os of adjacent dice. Tall copper pillars with a pitch of about 130 micrometers are grown underneath the RDLs. Because the majority of the I/O interconnections are between adjacent dice and have been connected by the silicon bridge, fewer I/Os need to be routed to the next level of interconnect with 130 micrometer bump pitch, which is achieved with tall copper-pillar bumping onto a standard substrate for flip-chip assembly.

The RDLs will merge power and ground micro-bumps with 40-50 micrometer bump pitch, reducing the number of power and ground bumps with tall copper pillars suitable for 130 micrometer bump pitch density. These bumps may also be assembled onto a standard organic or laminate substrate for flip-chip assembly.

The second option (Option 2 above) is a “chip last” service that handles die-to-die interconnects with less interconnection routing density. As the routing density reduces, the die-to-die interconnects no longer require a silicon bridge to pack so many traces onto a small area. This allows the removal of the silicon bridge, using only the RDL traces as the die-to-die interconnects between adjacent silicon dice. With the removal of the silicon bridge from the bump pitch transformer, the interposer cost in this option is lowered compared to the first option.

Sarcina’s BPT service offering includes BPT interposer design, O/S test pattern insertion, fabrication, BPT wafer sort, package substrate design, power/signal integrity, thermal system simulation, and substrate fabrication. A complete WIPO (wafer in, package out) engagement also covers wafer sort, package assembly, final test, qualification, and production services.

To Learn More

You can see the Bump Pitch Transformer announcements from Sarcina here and here. You can also learn more about this unique company on SemiWiki here. And you can get a broad view of Sarcina’s advanced packaging design services here. In a past life, I was involved in several advanced 2.5D package designs. I can tell you it’s nowhere near as easy as it may look. You really need a partner like Sarcina to tip the odds in your favor. I highly recommend you take a look.