While semiconductor design intellectual property (IP) is a $9.45 billion market, it acts as the absolute architectural bottleneck for the entire global semiconductor value chain. The choices made at the IP layer today dictate the cost, power, and security of a downstream technology economy rapidly marching toward a trillion… Read More
HBM’s Vertical Ascent: Why Packaging Is Becoming the Heart of AI Memory
SK hynix’s Hot Chips 2026 presentation explains how High Bandwidth Memory (HBM) is evolving to meet the extraordinary memory requirements of artificial intelligence. Its central message is that future progress will depend not only on better DRAM circuits but also on advanced packaging, denser vertical integration, improved… Read More
Intel 18A-P Pushes RibbonFET and Backside Power Beyond the First Generation
Intel Foundry has a blog on LinkedIn that is worth a look. The blogs are by trusted Intel Foundry technical experts and are filled with content. I will cherry pick write a bit about them but be sure and subscribe to this, absolutely.
Intel 18A-P is not a new process node in the conventional sense. It is a performance-enhanced derivative… Read More
Intel’s 14A Is Winning the Race Against Defects
Intel’s next-generation 14A manufacturing process is showing unusually strong early progress, with defect density falling faster than the company expected. The improvement gives Intel a technical boost as it attempts to restore confidence in its manufacturing operation, win foundry customers and demonstrate that years… Read More
TSMC’s Overseas Fabs Are Paying Off
TSMC’s overseas fabrication strategy is beginning to deliver its intended return: not immediate cost parity with Taiwan, but manufacturable geographic redundancy, closer integration with major customers and access to subsidized capacity in strategically important markets. Arizona and Kumamoto are already producing … Read More
Crescent Island: Turning Memory Capacity into Agentic AI Throughput
Intel’s Crescent Island is a discrete data-center GPU designed for agentic AI inference, where performance is constrained by more than matrix arithmetic. Multi-step agents impose latency through repeated model calls and tool interactions, consume large memory capacity for weights and long-context key-value caches, and… Read More
AI-designed Chip Points Toward a Faster Future for Custom Silicon
Architect Labs says it has created Redwood, an AI accelerator designed and verified almost entirely by artificial intelligence in less than two weeks. If independently validated and successfully translated from a programmable prototype into manufactured silicon, the project could represent a major change in how computer… Read More
Huawei Can’t Shrink Its Chips, So It’s Folding Them
On May 25, Huawei semiconductor chief He Tingbo unveiled LogicFolding, an architecture intended to advance chip performance without relying on ever-smaller transistors. Presented alongside Huawei’s “Tau Scaling Law,” the approach prioritizes signal speed over transistor dimensions. It is a genuine engineering response… Read More
Intel Diamond Rapids: Building Xeon Up, Out, and Through Silicon
Akhilesh Kumar & Krishnakanth Sistla, Intel
Diamond Rapids is Intel’s next-generation Xeon processor, designed around the proposition that hyperscale performance increasingly depends on moving, processing, and protecting data as efficiently as executing instructions. The architecture replaces the conventional… Read More
Intel Wildcat Lake: Right-Sizing Silicon Without Sinking Performance
Lance Hacking, Intel
Intel Core Series 3, code-named Wildcat Lake, is a mainstream client system-on-chip derived from the Panther Lake-based Core Ultra Series 3 architecture. Its design objective is not maximum feature density, but broad deployment of current-generation CPU, graphics, AI, memory, security, and connectivity… Read More


ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance