Webinar: RF design success hinges on enhanced models and accurate simulationTraditional RF board design strategies based on circuit…Read More
Arteris Raises Bar Again with AI-Based NoC DesignModern semiconductor devices, a far cry from the…Read More
2025 Outlook with Veerbhan Kheterpal of QuadricQuadric Inc. is the leading licensor of general-purpose…Read More
Samtec Advances Multi-Channel SerDes Technology with Broadcom at DesignConThere were many announcements and significant demonstrations of…Read More
On Wednesday at #60DAC I met Sudhir Mallya, Sr. VP Corporate Marketing at Alphawave Semi to get an update about what’s been happening at their IP company and with industry trends. The tagline for their company is: Accelerating the Connected World; and they have IP for connectivity, offer chiplet solutions, and even provide… Read More
Accellera sponsored a luncheon panel discussion at #60DAC, so I registered and attended to learn more about one of the newest working groups for Clock Domain Crossing (CDC). An overview of Accellera was provided by Lu Dai, then the panel discussion was moderated by Paul McLellan of Cadence, with the following panel members:
With metal interconnect pitches shrinking in advanced technology nodes, the center-to-center (C2C) separations between vias are also expected to shrink. For a 5/4nm node minimum metal pitch of 28 nm, we should expect vias separated by 40 nm (Figure 1a). Projecting to 3nm, a metal pitch of 24 nm should lead us to expect vias separated… Read More
I had grown comfortable thinking about RISC-V as a cost-saving and more flexible alternative to Intel/AMD or Arm in embedded applications. Where clearly it is already doing very well. But following a discussion with Dave Kelf and Adnan Hamid of Breker, RISC-V goals have become much more ambitious, chasing the same big system applications… Read More
Matt Genovese is the founder of Planorama Design, a software requirements and user experience design professional services company. The company designs simple and intuitive software and IoT product user interfaces for complex, technical applications and systems. Its unique and proven approach reduces client development… Read More
Chris Morrison, Director of Product Marketing at Agile Analog met with me on the Tuesday at DAC this year, and I asked what has changed in the last year for their analog IP business. The short answer is that the company has initially built up foundation IP for Analog Mixed-Signal (AMS) uses, then recently added new IP for data conversion,… Read More
A little thinking outside the box this time. Microsoft is adding automation to their (and LinkedIn) code reviews; maybe we should consider this option also? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series… Read More
Dan is joined by Dr. Adam Carter, CEO of OpenLight. Adam has over 25 years of experience in the semiconductor industry, including a variety of roles in Networking, Optical Communication Systems, Optical Components and Modules markets.
Adam describes OpenLight’s unique silicon photonics platform – what makes … Read More
Silicon Catalyst is the world’s only incubator focused exclusively on semiconductor solutions. This unique position puts the organization in the center of many new technology innovations. Recently, a Semiconductor Startups Contest was announced in collaboration with Arm. You can learn more about the details of the… Read More
At SEMICON West I had a chance to catch up with Mike Lercel of ASML. In this article I am going to combine ASML presentation material from the SPIE Advanced Lithography Conference, Mike’s SEMICON presentation, my discussions with Mike at SEMICON and a few items from ASML’s recent earnings call.
ASML continues to improve DUV systems.… Read More
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Rethinking Multipatterning for 2nm Node