I will see you at the Substrate Vision Summit in Santa ClaraWIth packaging being one of the top sources…Read More
The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)The Impact of AI on Software and Hardware…Read More
Alchip is Paving the Way to Future 3D Design InnovationAt the recent TSMC OIP Ecosystem Forum in…Read More
In my last article I talked about the physical design aspect of 3D-IC. Now looking at its verification aspect, it spans through a wide spectrum of test at hardware as well as software level. The verification challenge goes much beyond that of a SoC which is at a single plane. Even a typical SoC that comprises of a processor core, memory… Read More
The launch from Cadence of the PCI Express 3.0 Controller IP was officially done about one year ago, and demonstrated at the June 2011 PCI-SIG Developer’s Conference, where Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller… Read More
Holman Jenkins, the distinguished writer of business trends for the Wall St. Journal, recently penned an article entitled “The End of Apple’s Roach Motel?” (Personally, I think that since Apple is in California, he should have used Hotel California in his title), questioning the iPhone and iPAD maker of its ability to continue… Read More
John Stabenow is the marketing group director at Cadence for the Virtuoso products and it has been awhile since we last talked, so we met for lunch on Friday at McMenamins in a city called West Linn, half-way between where we both live in Oregon. I had blogged about Interoperability at DAC 2010 and we had a public exchange at Chip Design… Read More
Even though my Dresden trip was fraught with fail points it went off without a hitch. Flying over was easy, I connected through London Heathrow, flying back I connected through Frankfurt. The last time I connected through Frankfurt was right after the 9/11 attacks so I had a bit of deja vu. I was in Munich, Heathrow was closed, I was … Read More
Every year in Monterey is a relatively small conference that looks at the design process, EDPS, the electronic design process symposium. I gave a keynote there a couple of years ago, but you don’t have to listen to me this time. The keynotes are from:
I went to a couple more sessions at the Common Platform Technology Forum today, on 20nm double patterning and whatever will we do at 14nm. Basically, this is the end of planar transistors and the end of optical lithography. One session was by IBM scientists about process and one by Michael White of Mentor about double patterning. … Read More
I ask my customers about their cloud strategy and they all tell me “none”. The main reason is a red herring: “The legal department will never allow our IP outside our walls”.
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There were keynotes from all three semiconductor partners in the Common Platform Alliance and, as if to show how common they are, they all talked about the problems that need to be addressed in the next decade and a half and they all said pretty much the same thing. Gary Patton of IBM went first and so he got to say everything first. Plus,… Read More
I decided to attend a webinar today hosted by Synopsys, “Streamline Your PrimeTime ECO Flow For Fastest Setup, Hold and Timing DRC Closure.” The format was to present slides first then hold for questions until the end. Enough time was spent on questions which made this webinar different than most other webinars I’ve… Read More
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