Last week, Efabless announced the second edition of its AI Generated Open-Source Silicon Design Challenge series. As we discussed in earlier blogs, the first challenge was a great success with twelve submissions and six successful designs created in just three weeks. The contestants used natural language prompts to create… Read More
Reducing Electronic Systems Design Complexity with AI
In the world of electronic systems design, complexity has always been a major challenge. As technology advances and demands for more efficient and powerful electronic devices grow, engineers face increasingly intricate design requirements. These complexities often lead to longer design cycles, increased costs, … Read More
Has Electronics Bottomed?
The current slump in the electronics market began in 2021. Smartphone shipments versus a year earlier turned negative in 3Q 2021. The smartphone market declines in 2020 were primarily due to COVID-19 related production cutbacks. The current smartphone decline is due to weak demand. According to IDC, smartphone shipments were… Read More
WEBINAR: Driving Golden Specification-Based IP/SoC Development
The ever-increasing demands placed on Intellectual Property (IP) and System-on-Chip (SoC) development teams have resulted in an ever-increasing need for automation solutions that can boost productivity without contributing to further risk. Certainly, demands for automation have long been the drivers behind the growth… Read More
Back to Basics – Designing Out PPA Risk
I wrote earlier about managing service-level risk in SoC design, since the minimum service level a system can guarantee under realistic traffic is critical to OEM guarantees of dependable system performance. An ABS design which might get bogged down in traffic under only 0.1% of scenarios is of no use to anyone. That said, meeting… Read More
Points teams should consider about securing embedded systems
Wishful thinking once prevailed that embedded systems, especially small embedded devices, rarely needed security, and if they did, simply installing a “secure” operating system or a security chip would keep them safe. Connecting devices big and small on the Internet of Things (IoT) shattered such insular thinking… Read More
Analog Circuit Migration and Optimization
The MunEDA User Group Meeting (MUGM) has been an annual event since 2006, and this year there were some 80 participants from many customers that attended to share their experiences and learn how to get the best EDA tool results. I’ve been able to view the presentations and archived videos, so will share some of the interesting… Read More
Calibre’s next move – Correct-by-Construction IC Layout Optimization
Siemens EDA’s next move in its Calibre shift left strategy is the addition of correct-by-construction IC layout optimization for the most critical emerging physical design challenges. Calibre’s new DesignEnhancer product supports both custom and digital ICs and is already in use by several leading IC design companies. It … Read More
The Inconvenient Truth of Clock Domain Crossings
Almost everything that we do in chip design and verification was invented to raise the abstraction above schematics and polygons. Register-transfer-level (RTL) design, functional simulation, logic synthesis, floorplanning, and more fall into this category. Even the notion of binary circuits is an abstraction. Underneath… Read More
SEMICON West 2023 Summary – No recovery in sight – Next Year?
-SEMICON well attended but bouncing along the biz bottom
-Recovery seems at least a year away with memory even more
-AI creates hope but not impactful- Disconnect tween stocks & reality
-AMAT me too platform- Back end benefits from chiplets
SEMICON busy but subdued
SEMICON is certainly back to pre-covid levels or perhaps better.… Read More
5 Expectations for the Memory Markets in 2025