Linear pluggable optics target data center energy savingsData center density continues growing, driving interconnect technology…Read More
Bird’s Eye View Magic: Cadence Tensilica Product Group Pulls Back the CurtainEven for experienced technologists some technologies can seem…Read More
Siemens EDA Offers a Comprehensive Guide to PCIe® Transport SecurityIt is well-known that there is more data…Read More
Register Transfer Level (RTL) is a crucial and valuable concept in digital hardware design. Over the years, it has played a fundamental role in enabling design of complex digital chips. By abstracting away implementation details and providing a clear description of digital behavior, RTL has contributed significantly to the… Read More
DVCon India 2023 | Keynote: “Journeying Beyond AI: Unleashing the Art of Verification” by Sivakumar P R, Founder & CEO, Maven Silicon
Get Ready for an Epic Tech Odyssey with the keynote, ‘Journeying Beyond AI: Unleashing the Art of Verification’, by P. R. Sivakumar, Founder, and CEO, Maven Silicon.
The semiconductor industry… Read More
For decades, the concept of flying cars has captivated our imagination, fueling visions of a future where we can soar above the ground, free from the constraints of traffic and congestion. While once considered purely the stuff of science fiction, recent advancements in technology have brought us closer to turning this fantasy… Read More
Paul Cunningham from Cadence presented at the #60DAC Pavilion and gave one of the most optimistic visions of AI applied to EDA that I’ve witnessed, so hopefully I can convey some of his enthusiasm and outright excitement in my blog report. Mr. Cunningham reviewed the various ages of EDA design with each era providing about… Read More
Now that semiconductors are front page news and a political football, I would like to write more about how we got to where we are today to better understand where semiconductors will go tomorrow. I will start this article with a provocative quote that really made me laugh and will put some context to what I am trying to accomplish here:… Read More
Dan is joined by Chris Shrope. Chris leads high tech product marketing at Model N, a compliance leader for high-tech manufacturers. Chris has deep experience defining product market fit and related new product development activities. He received his MBA and holds certifications in Economics, Law, Product Management and Marketing.… Read More
Harry Peterson is a mixed-signal chip designer with a BS in Physics from Caltech. He managed IC design groups within Fairchild, Kodak, Philips, Northern Telecom, Toshiba and Pixelworks. During sabbaticals he helped fly experiments on NASA’s orbiting satellite observatory (OSO-8) and build telescopes in the Canary… Read More
On Wednesday at #60DAC I met Sudhir Mallya, Sr. VP Corporate Marketing at Alphawave Semi to get an update about what’s been happening at their IP company and with industry trends. The tagline for their company is: Accelerating the Connected World; and they have IP for connectivity, offer chiplet solutions, and even provide… Read More
Accellera sponsored a luncheon panel discussion at #60DAC, so I registered and attended to learn more about one of the newest working groups for Clock Domain Crossing (CDC). An overview of Accellera was provided by Lu Dai, then the panel discussion was moderated by Paul McLellan of Cadence, with the following panel members:
With metal interconnect pitches shrinking in advanced technology nodes, the center-to-center (C2C) separations between vias are also expected to shrink. For a 5/4nm node minimum metal pitch of 28 nm, we should expect vias separated by 40 nm (Figure 1a). Projecting to 3nm, a metal pitch of 24 nm should lead us to expect vias separated… Read More
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