Primarius 2B

Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points

Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points
by Daniel Payne on 11-02-2023 at 10:00 am

Worst case point min

IC designers are tasked with meeting specifications like robustness in SRAM bit cells where the probability of a violation are lower than 1 part-per-billion (1 ppb). Another example of robustness is a Flip-Flop register that must have a probability of specification violation lower than 1 part-per-million (1 ppm). Using Monte… Read More


Arm Total Design Hints at Accelerating Multi-Die Activity

Arm Total Design Hints at Accelerating Multi-Die Activity
by Bernard Murphy on 11-02-2023 at 6:00 am

multi die

I confess I am reading tea leaves in this blog, but why not? Arm recently announced Arm Total Design, an expansion of their Compute Subsystems (CSS) offering which made me wonder about the motivation behind this direction. They have a lot of blue-chip partners lined up for this program yet only a general pointer to multi-die systems… Read More


Generative AI for Silicon Design – Article 2 (Debug My Waveform)

Generative AI for Silicon Design – Article 2 (Debug My Waveform)
by Anshul Jain on 11-01-2023 at 10:00 am

Generative AI for Silicon Design Article 2

Generative AI has been making waves across various industries, and its potential continues to expand. Among its many applications, one particularly intriguing area is the capacity of GenAI to explain digital design waveforms and act as a co-pilot for hardware engineers in the debugging process. In this article, we will explore

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WEBINAR: How to Achieve 95%+ Accurate Power Measurement During Architecture Exploration

WEBINAR: How to Achieve 95%+ Accurate Power Measurement During Architecture Exploration
by Daniel Nenni on 11-01-2023 at 6:00 am

AVFS IP SOC

Today’s power modeling solutions are trained at measuring power using the micro-events captured from detailed RTL simulation or studying the electromagnetic radiation from IR drop and side channel attacks. These solutions are fantastic for debugging and verification of the implementation. There are both open source and … Read More


The Significance of Point Spread Functions with Stochastic Behavior in Electron-Beam Lithography

The Significance of Point Spread Functions with Stochastic Behavior in Electron-Beam Lithography
by Fred Chen on 10-31-2023 at 10:00 am

Electron Beam Lithography

Electron beam lithography is commercially used to directly write submicron patterns onto advanced node masks. With the advent of EUV masks and nanometer-scale NIL (nanoimprint lithography), multi-beam writers are now being used, compensating the ultralow throughput of a single high-resolution electron beam with the use… Read More


DVCon Europe is Coming Soon. Sign Up Now

DVCon Europe is Coming Soon. Sign Up Now
by Bernard Murphy on 10-31-2023 at 6:00 am

logo accellera min

I’m a fan of DVCon, a fan of Accellera and a fan of Munich, hosting DVCon Europe once again. This year’s event runs from November 14th through 15th (with some events on the 16th) at the Holiday Inn Munich in the City Center. Phillippe Notton (CEO, SiPearl) will deliver a keynote on “Energy Efficient High-Performance Computing in the… Read More


S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor

S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor
by Daniel Nenni on 10-30-2023 at 10:00 am

Pic1

S2C announced that the Beijing Institute of Open Source Chip (BOSC) adopted its Prodigy S7-19P Logic System, a VU19P-based FPGA prototyping solution, in the development of the “XiangShan” RISC-V processor. S7-19P not only accelerates the iterations of processor development but also simplifies other companies to realize … Read More


Developing Effective Mixed Signal Models. Innovation in Verification

Developing Effective Mixed Signal Models. Innovation in Verification
by Bernard Murphy on 10-30-2023 at 6:00 am

Innovation New

Mixed-signal modeling is becoming more important as interaction between digital and analog circuitry become more closely intertwined. This level of modeling depends critically on sufficiently accurate yet fast behavioral models for analog components. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano… Read More


KLAC- OK quarter in ugly environment- Big China $ – Little Process $ – Legacy good

KLAC- OK quarter in ugly environment- Big China $ – Little Process $ – Legacy good
by Robert Maire on 10-29-2023 at 10:00 am

KLAC Tencor
  • KLA has an OK quarter in an ugly market- bouncing along bottom
  • Like Lam & ASML, China was huge at 43% represents more risk
  • 2/3 Foundry/logic, 1/3 memory – Process tools were weak
  • No change, stable , no visibility on recovery
Quarter and guide were good in continued ugly industry

As expected KLAC reported earnings at the … Read More


Podcast EP190: The Growth and Impact of RISC-V and a Peek at the Upcoming RISC-V Summit with Calista Redmond

Podcast EP190: The Growth and Impact of RISC-V and a Peek at the Upcoming RISC-V Summit with Calista Redmond
by Daniel Nenni on 10-27-2023 at 10:00 am

Dan is joined by Calista Redmond, CEO of RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including vice president of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement… Read More