Bug Hunting in Multi Core Processors. Innovation in VerificationWhat’s new in debugging multi-/many-core systems? Paul Cunningham…Read More
Synopsys Expands Hardware-Assisted Verification Portfolio to Address Growing Chip ComplexityLast week, Synopsys announced an expansion of their…Read More
How Synopsys Enables Gen AI on the EdgeArtificial intelligence and machine learning have undergone incredible…Read More
Harnessing Modular Vector Processing for Scalable, Power-Efficient AI AccelerationThe dominance of GPUs in AI workloads has…Read More
CHIPS Act dies because employees are fired - NIST CHIPS people are probationary- NIST to lose 100's of mainly CHIPS…Read More
As the Design Automation Conference (DAC) approaches, anticipation builds for what promises to be an exceptional event in San Francisco. Attendees can look forward to perfect weather and a plethora of activities beyond the conference, such as sailing on the bay and exploring the city’s iconic landmarks.
Since its inception… Read More
DAC starts June 24th and I can already feel the buzz of excitement building up as I receive updates from EDA vendors like Keysight EDA. Talking with Scott Seiden, Director Strategic Marketing, Keysight EDA Portfolio, I learned that they have the largest booth on the first floor, now that’s a statement that caught my attention. This… Read More
Analog Bits, the industry’s leading provider of low-power mixed-signal IP solutions will be demonstrating several IP’s in TSMC advanced nodes at DAC. Analog Bits is also a long time DAC supporter and very active in the semiconductor and on SemiWiki, absolutely. Great company!
As power management and energy efficiency is getting… Read More
Dan is joined by Ninad Huilgol, founder and CEO at Innergy Systems. Ninad has extensive experience in design verification of ultra low-power mobile SoCs. Previously, he has worked in senior engineering management at various semiconductor companies such as Broadcom and Synopsys. He has multiple power- and design-related patents,… Read More
The Silicon Catalyst-Arm start-up contest winners were announced this week. This was the first contest of its kind so there was quite a bit of excitement. SemiWiki has worked closely with Silicon Catalyst for the past four years which has been quite the journey. Out of the one hundred plus companies SemiWiki has worked with over … Read More
Introduction of 2.5D and 3D multi-die based products are helping extend the boundaries of Moore’s Law, overcoming limitations in speed and capacity for high-end computational tasks. In spite of its critical function within the 3DIC paradigm, the interposer die’s role and related challenges are often neither fully comprehended… Read More
Recently, a partnership between Achronix and Bluespec has been in the news. Bluespec RISC-V processors are available as soft cores in a Speedster®7t FPGA on Achronix’s VectorPath® PCIe development card or in a standalone Speedster7t FPGA. We spoke with executives from Achronix and Bluespec about the impetus for this effort … Read More
Peter was running late for two reasons. First, he encountered unexpected heavy traffic and arrived ten minutes late for a crucial meeting with a customer to run a compliance test of his new 6G phone design prototyped on FPGAs. This prototype’s success was pivotal, as it could secure a significant purchase order.… Read More
Given false starts and OEM strategic retreats you could be forgiven for thinking that the autonomous personal car dream is now a lost cause. But that’s not quite true. While moonshot goals have been scaled back or are running under wraps, applications continue to advance, for adaptive cruise control, collision avoidance, automatic… Read More
As SoC complexities continue to expand to billions of transistors, the quest for higher levels of design automation also rises. This has led to the adoption of High-Level Synthesis (HLS), using design languages such as C++ and SystemC, which is more productive than traditional RTL design entry methods. In the RTL approach there… Read More
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Unlocking the cloud: A new era for post-tapeout flow for semiconductor manufacturing