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System Technology Co-Optimization (STCO)

System Technology Co-Optimization (STCO)
by Daniel Payne on 11-30-2021 at 10:00 am

An early package prototype

My first exposure to seeing multiple die inside of a single package in order to get greater storage was way back in 1978 at Intel, when they combined two 4K bit DRAM die in one package, creating an 8K DRAM chip, called the 2109. Even Apple used two 16K bit DRAM chips from Mostek to form a 32K bit DRAM, included in the Apple III computer, circa… Read More


High-Performance Natural Language Processing (NLP) in Constrained Embedded Systems

High-Performance Natural Language Processing (NLP) in Constrained Embedded Systems
by Kalar Rajendiran on 11-30-2021 at 6:00 am

Demonstrator Block Diagram

Current technology news is filled with talk of many edge applications moving processing from the cloud to the edge. One of the presentations at the recently concluded Linley Group Fall Processor Conference was about AI moving from the cloud to the edge. Rightly so, there were several sessions dedicated to discussing AI and edge… Read More


Siemens EDA will be returning to DAC this year as a Platinum Sponsor.

Siemens EDA will be returning to DAC this year as a Platinum Sponsor.
by Daniel Nenni on 11-29-2021 at 10:00 am

Siemens EDA DAC

The 38th Design Automation Conference is next week and this one is for the record books. Having been virtual the last two years, next week we will meet live once again. I think we may have all taken for granted the value of live events but now we know how important they are on both a professional and human level, absolutely.

“The… Read More


Silicon Catalyst Hosts an All-Star Panel December 8th to Discuss What Happens Next?

Silicon Catalyst Hosts an All-Star Panel December 8th to Discuss What Happens Next?
by Mike Gianfagna on 11-29-2021 at 6:00 am

Silicon Catalyst Hosts an All Star Panel December 8th to Discuss What Happens Next

Each year, Silicon Catalyst assembles a panel of industry luminaries to discuss important questions about the future. The charter of the Silicon Catalyst Industry Forum is to: “create a platform for broad-topic dialog among all stakeholders involved in the semiconductor industry value chain. The Forum topics focus on technicalRead More


Big Data Helps Boost PDN Sign Off Coverage

Big Data Helps Boost PDN Sign Off Coverage
by Tom Simon on 11-28-2021 at 8:00 am

PDN Sign Off

The nearly unavoidable truth about dynamic voltage drop (DVD) signoff for power distribution networks (PDN) is that the quality of results depends on the quality and quantity of the vectors used to activate the circuit switching. As SOCs grow larger and are implemented on smaller nodes, the challenges of sufficient coverage … Read More


Empyrean Technology‘s Complete Design Solution for PMIC

Empyrean Technology‘s Complete Design Solution for PMIC
by Daniel Nenni on 11-28-2021 at 6:00 am

PMIC Design SemiWIki

Power management integrated circuits (PMICs) are integrated circuits for power management. Driven by the strong demand in consumer electronics, IoT, and the automobile industry, the design for PMIC is getting more challenging in terms of integration, reliability and efficiency. The design methodology needs to be updated… Read More


Podcast EP50: What happens next in the CPU and GPU wars?

Podcast EP50: What happens next in the CPU and GPU wars?
by Daniel Nenni on 11-26-2021 at 10:00 am

Tom is the creator of the Moore’s Law Is Dead YouTube Channel and Broken Silicon podcast. He creates videos and writes articles containing in-depth commentary and analysis of what’s going on in Technology, Gaming, and Computer Hardware; and also recaps the news and interviews people working within the gaming &… Read More


CEO Interview: Pradeep Vajram of AlphaICs

CEO Interview: Pradeep Vajram of AlphaICs
by Daniel Nenni on 11-26-2021 at 6:00 am

Pradeep Pic 2020

Pradeep Vajram is a successful entrepreneur and a veteran in the Semiconductor / Embedded industry. He has over 25+ years of experience in having executed, at all levels of responsibilities, in design and development of ASIC products.

Pradeep has been an active investor in semiconductor and deep tech USA-INDIA corridor start-up,… Read More


PCIe Gen5 Interface Demo Running on a Speedster7t FPGA

PCIe Gen5 Interface Demo Running on a Speedster7t FPGA
by Kalar Rajendiran on 11-24-2021 at 10:00 am

PCIe Gen5 Interface Demo Board

The major market drivers of today all have one thing in common and that is the efficient management of data. Whether it is 5G, hyperscale computing, artificial intelligence, autonomous vehicles or IoT, there is data creation, processing, transmission and storage. All of these aspects of data management need to happen very fast.… Read More


WEBINAR: Using Design Porting as a Method to Access Foundry Capacity

WEBINAR: Using Design Porting as a Method to Access Foundry Capacity
by Tom Simon on 11-24-2021 at 8:00 am

Schematic Porting the NanoBeacon

There have always been good reasons to port designs to new foundries or processes. These reasons have included reusing IP in new projects, moving an entire design to a smaller node to improve PPA, or second sourcing manufacturing. While there can be many potential business motivations for any of the above, in today’s environment… Read More