At #61DAC, I love it when an exhibitor booth uses a descriptive tagline to explain what they do, like when the Blue Cheetah booth displayed Advancing Chiplet Interconnectivity. Immediately, I knew that they were an IP provider focusing on chiplets. I learned what sets them apart is how customizable their IP is to support specific… Read More
The China Syndrome- The Meltdown Starts- Trump Trounces Taiwan- Chips Clipped
- The chip industry got a double tap of both China & Taiwan concerns
- Bloomberg reported the potential for draconian China chip restrictions
- Trump threw Taiwan under the bus demanding “protection money”
- Over-inflated chip stocks had a “rapid unscheduled disassembly”
US looking to further restrict
… Read MoreEvolution of Prototyping in EDA
As AI and 5G technologies burgeon, the rise of interconnected devices is reshaping everyday life and driving innovation across industries. This rapid evolution accelerates the transformation of the chip industry, placing higher demands on SoC design. Moore’s Law indicates that while chip sizes shrink, the number of… Read More
How Sarcina Revolutionizes Advanced Packaging #61DAC
#61DAC was buzzing with discussion of chiplet-based, heterogeneous design. This new design approach opens new opportunities for applications such as AI, autonomous driving and even quantum computing. A critical enabler for all this to work is reliable, cost-effective advanced packaging, and that is the topic of this post.… Read More
Accelerating Analog Signoff with Parasitics
An under-appreciated but critical component in signing off the final stage of chip design for manufacture is timing closure – aligning accurate timing based on final physical implementation with the product specification. Between advanced manufacturing processes and growing design sizes, the most important factors determining… Read More
Scientific Analog XMODEL #61DAC
Transistor-level circuit designers have long used SPICE for circuit simulation, mostly because it is silicon accurate and helps them to predict the function, timing, power, waveforms, slopes and delays in a cell before fabrication. RTL designers use digital simulators that have a huge capacity but are lacking analog modeling.… Read More
PCIe design workflow debuts simulation-driven virtual compliance
PCIe design complexity continues rising as the standard for intrasystem communication evolves. An urgent need for more system bandwidth drives PCIe interconnects to multi-lane, multi-link, multi-level signaling. Classical PCIe design workflows leave designers with most of the responsibility for getting the requisite… Read More
The Immensity of Software Development the Challenges of Debugging (Part 1 of 4)
Part 1 of this 4-part series introduces the complexities of developing and bringing up the entire software stack on a System on Chip (SoC) or Multi-die system. It explores various approaches to deployment, highlighting their specific objectives and the unique challenges they address.
Introduction
As the saying goes, it’s… Read More
Codasip Makes it Easier and Safer to Design Custom RISC-V Processors #61DAC
RISC-V continued to be a significant force at #61DAC. There were many events that focused on its application in a wide variety of markets. As anyone who has used an embedded processor knows, the trick is how to be competitive. Using the same core as everyone else and differentiating in software is a strategy that tends to run out of … Read More
Podcast EP235: Tinier than TinyML: pushing the flexible boundaries of AI – Pragmatic Semiconductor
Dan is joined by Dr. Richard Price, CTO and Dr. Konstantinos Iordanou, a senior ASIC designer at Pragmatic Semiconductor.
Richard has over 25 years’ experience in the development and commercialisation of a wide range of new technologies based on novel processes, materials and flexible electronics. Richard is also a non-executive… Read More
Build a 100% Python-based Design environment for Large SoC Designs