In the world of semiconductor design, constraints are essentially specifications and requirements that guide the implementation of a specific hardware or software component within a larger system. They dictate timing, area, power, performance, and of course functionality of a design, playing a crucial role in ensuring that… Read More
Curbing Soaring Power Demand Through Foundation IPPower has become a very hot (ha-ha) topic.…Read More
2026 Outlook with Badru Agarwala of Rise Design Automation (RDA)Badru Agarwala is the CEO and Co-Founder of…Read More
2026 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDACristian Amitroaie is the Founder and CEO of…Read More
Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V ExtensionThe rapid growth of signal processing workloads in…Read More
2026 Outlook with Richard Hegberg of Caspia TechnologiesTell us a little bit about yourself and…Read MoreWEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems
Nowadays, low power design requirements are key for large SoCs (system on chips) for different applications: AI, Mobile, HPC, etc. Power intent management early in the design flow is becoming crucial to help facing PPA (Power Performance Area) design challenges.
With the increasing complexity of such … Read More
The First Automotive Design ASIC Platform
Alchip Technologies, Ltd. is a company that specializes in ASIC (Application-Specific Integrated Circuit) design and manufacturing. They are known for providing high-performance and customized ASIC solutions for a variety of applications. Alchip works with clients to design and develop integrated circuits that meet specific… Read More
UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem
Intel recently made headlines when CEO Pat Gelsinger unveiled the world’s first UCIe interoperability test chip demo at Innovation 2023. The test chip built using advanced packaging technology is codenamed Pike Creek and is used to demonstrate interoperability across chiplets designed by Intel and Synopsys. More details … Read More
IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation
For more than 65 years, the IEEE International Electron Devices Meeting (IEDM) has been the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. As I post this, the conference is underway in San Francisco… Read More
Podcast EP197: A Tour of the RISC-V Movement and SiFive’s Contributions with Jack Kang
Dan is joined by Jack Kang of SiFive. As a member of the founding team at SiFive, Jack oversees the Business Development, Customer Experience, and Corporate Marketing groups. He is responsible for strategic business initiatives and partnerships, technical pre-sales activities and post-sales support, and corporate messaging… Read More
CEO Interview: Suresh Sugumar of Mastiska AI
Suresh is a technology executive with deep technical expertise in semiconductors, artificial intelligence, cybersecurity, internet-of-things, hardware, software, etc. He spent 20 years in the industry, most recently serving as an Executive Director for open-source zero-trust chip development at Technology Innovation… Read More
Analysis and Verification of Single Event Upset Mitigation
The evolution of space-based applications continues to drive innovation across government and private entities. The new demands for advanced capabilities and feature sets have a direct impact on the underlying hardware, driving companies to migrate to smaller geometries to deliver the required performance, area, and power… Read More
5G Aim at LEO Satellites Will Stimulate Growth and Competition
Low earth orbit (LEO) satellites as an intermediary for communication became hot when Elon Musk announced Starlink (yeah, other options were available, but Elon Musk). This capability extends internet availability to remote areas and notably (for a while) to Ukraine in support of the war with Russia. Satellites can in principle… Read More
Do you have Time to Pull in your Tapeout Schedule?
So… , we’re 4 months before tapeout. You were assigned to close place & route on three complex key blocks. You have 15 machines for the job, 5 per block.
You send your first batch, 5 runs per block. You’re not very surprised that your first batch fails. You modify the scripts, and run another batch. And… (Surprise… Read More


AI Bubble?