Constrained random methods in simulation are universally popular, still can the method be improved? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.… Read More




Clock Verification for Mobile SoCs
The relentless advancement of mobile phone technology continues to push boundaries, demanding SoCs that deliver ever-increasing performance while preserving extensive battery life. To meet these demands, the industry is progressively embracing lower technology nodes with current designs being taped-out at 5nm or below.… Read More
Samsung Foundry on Track for 2nm Production in 2025
On the heels of the TSMC Symposium and the Intel Foundry update, Samsung held their Foundry Forum today live in Silicon Valley. As usual it was a well attended event with hundreds of people and dozens of ecosystem partners. The theme was the AI Era which is appropriate. As I have mentioned before, AI will touch most every chip and there… Read More
Keysight at #60DAC
Keysight EDA will have a large presence at this year’s DAC in San Francisco July 9-13. For a better understanding of what’s happening with Keysight EDA at DAC I talked to my contacts to learn that they have three main messages this year:
Demos: Booth 1531
You may recall that Keysight acquired Cliosoft… Read More
Transforming the electronics ecosystem with the component digital thread
The transformation of the vertically integrated electronics value chain to a disaggregated supply chain has brought tremendous value to the electronics industry and benefits to the consumers. This transformation has driven the various players to become highly specialized in order to support the market trends and demands … Read More
Ansys Revving up for Automotive and 3D-IC Multiphysics Signoff at DAC 2023
Highlights:
- Ansys CTO Prith Banerjee will be delivering the Visionary Speaker opening address on Tuesday 11th
- There will be technical presentations every hour in the Ansys Booth Theater (#1539)
- Get yourself a complimentary sit-down breakfast and a discussion on automotive electronics by registering for the Ansys DAC
Assessing EUV Wafer Output: 2019-2022
At the 2023 SPIE Advanced Lithography and Patterning conference, ASML presented an update on its EUV lithography systems in the field [1]. The EUV wafer exposure output was presented and is shown below in table form:
From this information, we can attempt to extract and assess the EUV wafer output per quarter. First, since there … Read More
Podcast EP166: How iDEAL Semiconductor is Revolutionizing Power Device Design & Manufacturing
Dan is joined by Ryan Manack, Vice President of Marketing for iDEAL Semiconductor. Prior to iDEAL Ryan spent 15 years at Texas Instruments which I consider one of the most influential companies in the history of semiconductors.
Ryan describes SuperQ, the unique core technology platform of iDEAL Semiconductor. Using the approach… Read More
Efabless Celebrates AI Design Challenge Winners!
The first AI Generated Open-Source Silicon Design Challenge invited participants to use generative AI to design an open-source silicon chip and tape it out in just three weeks. The contestants were required to create Verilog code from natural language prompts, and then implemented their designs using the chipIgnite platform… Read More
Optimism Prevailed at CEO Outlook, though Downturn Could Bring Unpredictable Challenges
Chances are anyone who attended the CEO Outlook will say it was an engaging, entertaining and enlightening view of the chip design space, though CEO Outlook may be a misnomer as four of the seven panelists had C-Suite titles other than CEO.
Regardless, the collective view was optimistic, though caution prevailed as the economic… Read More
Should Intel be Split in Half?