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Synopsys Debuts RISC-V IP Product Families

Synopsys Debuts RISC-V IP Product Families
by Bernard Murphy on 11-08-2023 at 6:00 am

Synopsys ARC V family min

Synopsys has just announced that it has expanded its ARC processor portfolio to include a family of RISC-V processors. These will be branded under the ARC name as ARC-V and are expected to become available in 2024. This is a significant announcement which I attempt to unpack briefly below.

Why add RISC-V to the portfolio and why now?

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WEBINAR: Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips

WEBINAR: Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
by Daniel Nenni on 11-07-2023 at 10:00 am

Webinar Image

The automotive industry imposes stringent requirements on Functional Safety. For semiconductor companies involved in automotive chips and even further upstream in Silicon Intellectual Property (SIP), obtaining ISO 26262 certification is a fundamental requirement for product penetration into automotive applications.… Read More


A Fast Path to Better ARC PPA through Fusion Quickstart Implementation Kits and DSO.AI

A Fast Path to Better ARC PPA through Fusion Quickstart Implementation Kits and DSO.AI
by Bernard Murphy on 11-07-2023 at 6:00 am

QIK+DSO.AI flow

Synopsys recently presented a webinar on using their own software to optimize one of their own IPs (an ARC HS68 processor) for both performance and power through what looks like a straightforward flow from initial configuration through first level optimization to more comprehensive AI-driven PPA optimization. Also of note … Read More


Unlocking the Power of Data: Enabling a Safer Future for Automotive Systems

Unlocking the Power of Data: Enabling a Safer Future for Automotive Systems
by Kalar Rajendiran on 11-06-2023 at 10:00 am

SDVs New Monetization Opportunities

The automotive industry is undergoing a major transformation; it is not about just connectivity and convenience anymore. Data is emerging as the driving force behind innovation and safety with vehicles becoming sophisticated data-driven machines. By unlocking the power of data, we can create safer vehicles and roads and usher… Read More


Make Your RISC-V Product a Fruitful Endeavor

Make Your RISC-V Product a Fruitful Endeavor
by Daniel Nenni on 11-06-2023 at 6:00 am

RISC V Chip

Consider RISC-V ISA as a new ‘unforbidden fruit’. Unlike other fruits (ISAs) that grow in proprietary orchards, RISC-V is available to all, i.e. open-source. Much like a delicious fruit can be transformed into a wide array of delectable desserts, so can RISC-V be utilized to create a plethora of effective applications across … Read More


Podcast EP191: The Impact of Evolving AI System Architectures and Samtec’s Role with Matt Burns

Podcast EP191: The Impact of Evolving AI System Architectures and Samtec’s Role with Matt Burns
by Daniel Nenni on 11-03-2023 at 10:00 am

Dan is joined by Matthew Burns, Matt develops go-to-market strategies for Samtec’s Silicon to Silicon solutions. Over the course of 20+ years, he has been a leader in design, technical sales and marketing in the telecommunications, medical and electronic components industries.

Matt and Dan discuss revelations from the recent… Read More


Executive Interview: Tony Casassa, General Manager of METTLER TOLEDO THORNTON

Executive Interview: Tony Casassa, General Manager of METTLER TOLEDO THORNTON
by Daniel Nenni on 11-03-2023 at 6:00 am

TC MT Thornton

Tony Casassa has served as the General Manager of METTLER TOLEDO THORNTON since 2015, after having joined the company in 2007 to lead the US Process Analytics business. Prior to spending the last 16 years with METTLER TOLEDO, Tony held various business leadership positions for 2 decades with Rohm and Haas Chemical. A common thread… Read More


Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points

Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points
by Daniel Payne on 11-02-2023 at 10:00 am

Worst case point min

IC designers are tasked with meeting specifications like robustness in SRAM bit cells where the probability of a violation are lower than 1 part-per-billion (1 ppb). Another example of robustness is a Flip-Flop register that must have a probability of specification violation lower than 1 part-per-million (1 ppm). Using Monte… Read More


Arm Total Design Hints at Accelerating Multi-Die Activity

Arm Total Design Hints at Accelerating Multi-Die Activity
by Bernard Murphy on 11-02-2023 at 6:00 am

multi die

I confess I am reading tea leaves in this blog, but why not? Arm recently announced Arm Total Design, an expansion of their Compute Subsystems (CSS) offering which made me wonder about the motivation behind this direction. They have a lot of blue-chip partners lined up for this program yet only a general pointer to multi-die systems… Read More


Generative AI for Silicon Design – Article 2 (Debug My Waveform)

Generative AI for Silicon Design – Article 2 (Debug My Waveform)
by Anshul Jain on 11-01-2023 at 10:00 am

Generative AI for Silicon Design Article 2

Generative AI has been making waves across various industries, and its potential continues to expand. Among its many applications, one particularly intriguing area is the capacity of GenAI to explain digital design waveforms and act as a co-pilot for hardware engineers in the debugging process. In this article, we will explore

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